Details, datasheet, quote on part number: MC10159
PartMC10159
CategoryLogic => Multiplexers/Demultiplexers => Bipolar->ECL 10 Family
TitleBipolar->ECL 10 Family
DescriptionQuad 2-input Multiplexer (inverting)
CompanyON Semiconductor
DatasheetDownload MC10159 datasheet
Cross ref.Similar parts: MC10159L, MC10159P
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Features, Applications

The is a quad two channel multiplexer with enable. It incorporates common enable and common data select inputs. The select input determines which data inputs are enabled. A high (H) level enables data inputs D10, D20, and D30. A low (L) level enables data inputs D11, D21, and D31. Any change on the data inputs will be reflected at the outputs while the enable is low. Input levels are inverted at the output. PD=218 mW typ/pkg (No Load) tpd=2.5 ns typ (Data to Q) 3.2 ns typ (Select to Q) tr, tf=2.5 ns typ (20%­80%)

SELECT D10 4 ENABLE WW = Assembly Location = Wafer Lot = Year = Work Week PLCC­20 FN SUFFIX CASE 775 VCC = PIN 16 VEE = PIN PDIP­16 P SUFFIX CASE AWLYYWW

Device MC10159P MC10159FN Package PDIP­16 PLCC­20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / Rail

Pin assignment is for Dual­in­Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D).

Characteristic Power Supply Drain Current Input Current
Output Voltage Output Voltage Threshold Voltage Threshold Voltage

Switching Times (50 Load) Propagation Delay Rise Time Fall Time Data Input Select Input Enable Input to 80%)

TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VILmin VIHAmin VILAmax VEE V
Output Voltage Output Voltage Threshold Voltage Threshold Voltage Switching Times Propagation Delay
Logic 1 Logic 0 Logic 1 Logic 0 (50 Load) Data Input Select Input Enable Input to 80%)

Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50­ohm resistor to ­2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.

PLCC­20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775­02 ISSUE C

NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).


 

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