Details, datasheet, quote on part number: MC10159P
PartMC10159P
CategoryLogic => Multiplexers/Demultiplexers => Multiplexers
TitleMultiplexers
DescriptionQuad 2-Input Multiplexer (Inverting) , Package: Pdip, Pins=16
CompanyON Semiconductor
DatasheetDownload MC10159P datasheet
Quote
Find where to buy
 
  

 

Features, Applications

The is a quad two channel multiplexer with enable. It incorporates common enable and common data select inputs. The select input determines which data inputs are enabled. A high (H) level enables data inputs D10, D20, and D30. A low (L) level enables data inputs D11, D21, and D31. Any change on the data inputs will be reflected at the outputs while the enable is low. Input levels are inverted at the output. PD=218 mW typ/pkg (No Load) tpd=2.5 ns typ (Data to Q) 3.2 ns typ (Select to Q) tr, tf=2.5 ns typ (20%­80%)

SELECT D10 4 ENABLE WW = Assembly Location = Wafer Lot = Year = Work Week PLCC­20 FN SUFFIX CASE 775 VCC = PIN 16 VEE = PIN PDIP­16 P SUFFIX CASE AWLYYWW

Device MC10159P MC10159FN Package PDIP­16 PLCC­20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / Rail

Pin assignment is for Dual­in­Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D).

Characteristic Power Supply Drain Current Input Current
Output Voltage Output Voltage Threshold Voltage Threshold Voltage

Switching Times (50 Load) Propagation Delay Rise Time Fall Time Data Input Select Input Enable Input to 80%)

TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VILmin VIHAmin VILAmax VEE V
Output Voltage Output Voltage Threshold Voltage Threshold Voltage Switching Times Propagation Delay
Logic 1 Logic 0 Logic 1 Logic 0 (50 Load) Data Input Select Input Enable Input to 80%)

Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50­ohm resistor to ­2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.

PLCC­20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775­02 ISSUE C

NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).


 

Some Part number from the same manufacture ON Semiconductor
MC10161 Binary to 1-8 Decoder (low)
MC10161FN Binary to 1-8 Decoder (Low) , Package: Plcc, Pins=20
MC10161FNR2 Binary to 1-8 Decoder (Low), Package: Plcc, Pins=20
MC10161P Binary to 1-8 Decoder (Low) , Package: Plcc, Pins=20
MC10162
MC10162FN Binary to 1-8 Decoder (High) , Package: Plcc, Pins=20
MC10162FNR2 Binary to 1-8 Decoder (High), Package: Plcc, Pins=20
MC10162P Binary to 1-8 Decoder (High) , Package: Plcc, Pins=20
MC10164 8-line Multiplexer
MC10164FN 8-Line Multiplexer , Package: Plcc, Pins=20
MC10164FNR2 8-Line Multiplexer, Package: Plcc, Pins=20
MC10164P 8-Line Multiplexer , Package: Plcc, Pins=20
MC10166 5-bit Magnitude Comparator
MC10171 Dual Binary to 1-4 Decoder (low)
MC10171FN Dual Binary to 1:4 Decoder (Low) , Package: Plcc, Pins=20
MC10171FNR2 Dual Binary to 1:4 Decoder (Low), Package: Plcc, Pins=20
MC10173 Quad 2-input Multiplexer/latch
MC10173L Quad 2-Input Multiplexer/Latch, Package: Cdip, Pins=16
MC10173P Quad 2-Input Multiplexer/latch , Package: Pdip, Pins=16
MC10174 Dual 4 to 1 Multiplexer
MC10174FN Dual 4:1 Multiplexer , Package: Plcc, Pins=20
Same catergory

74HC157 : Multiplexers. 74HC/HCT157; Quad 2-input Multiplexer;; Package: SOT109-1 (SO16), SOT338-1 (SSOP16), SOT38-4 (DIP16), SOT403-1 (TSSOP16).

AVGDV74HCT08AD : Quad 2 Input And Gate, Plastic Sop, Surface Mount.

DM74AS805B : Bipolar->AS Family. Hex 2-Input Nor Driver. These devices contain six independent drivers, each of which performs the logic NOR function. Each driver has increased output drive capability to allow the driving of high capacitive loads. s Switching s pF s Switching s guaranteed over full temperature and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL process s Functionally and pin for pin compatible.

DM74LS33 : Bipolar->LS Family. Quad 2-Input Nor Buffer With Open Collector Outputs.

SN54AS10FK : Triple 3-input Positive-nand Gates. Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs These devices contain three independent 3-input positive-NAND gates. They perform the Boolean functions or in positive logic. The SN54ALS10A and SN54AS10 are characterized for operation over the full military.

SN54HCT574 : Octal Edge-triggered D-type Flip-flops With 3-state Outputs. SN54HCT574, SN74HCT574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS Inputs Are TTL-Voltage Compatible High-Current 3-State Noninverting Outputs Drive Bus Lines Directly to 15 LSTTL Loads Bus-Structured Pinout Package Options Include Plastic Small-Outline (DW), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip.

SN54LS09FK : Quadruple 2-input Positive-and Gates With Open-collector Outputs.

SN74CBT16292 : Multiplexers. 12-bit 1-of-2 Fet Multiplexer/demultiplexer With Internal Pulldown Resistors.

SN74LS96 : Bipolar->LS Family. 5-bit Shift Registers.

SN74S195 : Bipolar->TTL Family. 4-bit Parallel Access Shift Register.

A3P060-1VQ100II : FPGA, 1536 CLBS, 60000 GATES, 350 MHz, PQFP100. s: System Gates: 60000 ; Logic Cells / Logic Blocks: 1536 ; Package Type: Other, 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, VQFP-100 ; Logic Family: CMOS ; Pins: 100 ; Internal Frequency: 350 MHz ; Operating Temperature: -40 to 85 C (-40 to 185 F) ; Supply Voltage: 1.5V.

M1AGL400V2-CS196 : FPGA, 9216 CLBS, 400000 GATES, PBGA196. s: System Gates: 400000 ; Logic Cells / Logic Blocks: 9216 ; Package Type: Other, 8 X 8 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, CSP-196 ; Logic Family: CMOS ; Pins: 196 ; Operating Temperature: 0 to 70 C (32 to 158 F) ; Supply Voltage: 1.2V.

XC5202-3PC84I : FPGA, 64 CLBS, 2000 GATES, 83 MHz, PQCC84. s: System Gates: 2000 ; Logic Cells / Logic Blocks: 64 ; Package Type: Other, PLASTIC, LCC-84 ; Logic Family: CMOS ; Pins: 84 ; Internal Frequency: 83 MHz ; Propagation Delay: 3 ns ; Supply Voltage: 5V.

 
0-C     D-L     M-R     S-Z