Details, datasheet, quote on part number: MC10162
PartMC10162
CategoryLogic => Decoders/Demultiplexers
Description
CompanyON Semiconductor
DatasheetDownload MC10162 datasheet
Cross ref.Similar parts: MC10162FN, MC10162FNR2, MC10162L
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Features, Applications

The MC10162 is designed to convert three lines of input data to a one­of­eight output. The selected output will be high while all other outputs are low. The enable inputs, when either or both are high, force all outputs low. The is a true parallel decoder. No series gating is used internally, eliminating unequal delay times found in other decoders. This device is ideally suited for demultiplexer applications. One of the two enable inputs is used as the data input, while the other is used as a data enable input. A complete mux/demux operation on 16 bits for data distribution is illustrated in Figure 1 of the MC10161 data sheet. 315 ns typ/pkg (No Load) tpd 4.0 ns typ tr, 2.0 ns typ (20%­80%)

CDIP­16 L SUFFIX CASE PDIP­16 P SUFFIX CASE PLCC­20 FN SUFFIX CASE 775 10162 AWLYYWW MC10162P AWLYYWW MC10162L AWLYYWW

= Assembly Location = Wafer Lot = Year = Work Week

Pin assignment is for Dual­in­Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D).

Device MC10162P MC10162FN Package PDIP­16 PLCC­20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / Rail

Characteristic Power Supply Drain Current Input Current
Output Voltage Output Voltage Threshold Voltage Threshold Voltage
Switching Times (50 Load) Propagation Delay Rise Time Fall Time to 80%)

Output Voltage Output Voltage Threshold Voltage Threshold Voltage Switching Times Propagation Delay Rise Time Fall Time

Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50­ohm resistor to ­2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.

PLCC­20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775­02 ISSUE C

NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).


 

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