|Category||Logic => Counters => Bipolar->ECL 10 Family|
|Title||Bipolar->ECL 10 Family|
|Datasheet||Download MC10178 datasheet
The is a fourbit counter capable of dividebytwo, dividebyfour, dividebyeight or a dividebysixteen function. Clock inputs trigger on the positive going edge of the clock pulse. Set and Reset inputs override the clock, allowing asynchronous "set" or "clear." Individual Set and common Reset inputs are provided, as well as complementary outputs for the first and fourth bits. True outputs are available at all bits. 370 mW typ/pkg (No Load) ftoggle=150 MHz (typ) tr, 2.7 ns typ (20%80%)CDIP16 L SUFFIX CASE PDIP16 P SUFFIX CASE 648 MC10178P AWLYYWW 1 10178 AWLYYWW MC10178L AWLYYWW
= Assembly Location = Wafer Lot = Year = Work Week
Pin assignment is for DualinLine Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D).
Device MC10178P MC10178FN Package PDIP16 PLCC20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / RailClock transition from VIL to VIH may be applied C2 or both for same effect.
Characteristic Power Supply Drain Current Input Current
IinL Output Voltage Output Voltage Threshold Voltage Logic 1 Logic 0 Logic 1 VOH VOL VOHA
Rise Time Fall Time Set Input Reset Input
* Individually test each input applying VIL to input under test.
Rise Time Fall Time Set Input Reset Input Counting Frequency
* Individually test each input applying IL to input under test. Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50ohm resistor to 2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.
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