|Category||Logic => Flip-Flops|
|Description||Hex D-type Master-slave Flip-flop With Reset, Package: Plcc, Pins=20|
|Datasheet||Download MC10186FNR2 datasheet
The MC10186 contains six highspeed, master slave type "D" flipflops. Clocking is common to all six flipflops. Data is entered into the master when the clock is low. Master to slave data transfer takes place on the positivegoing Clock transition. Thus, outputs may change only on a positivegoing Clock transition. A change in the information present at the data (D) input will not affect the output information any other time due to the masterslave construction of this device. A COMMON RESET IS INCLUDED IN THIS CIRCUIT. RESET ONLY FUNCTIONS WHEN CLOCK IS LOW. 460 mW typ/pkg (No Load) ftoggle = 150 MHz (typ) tr, 2.0 ns typ (20%80%)CDIP16 L SUFFIX CASE PDIP16 P SUFFIX CASE AWLYYWW MC10186P AWLYYWW MC10186L AWLYYWW
= Assembly Location = Wafer Lot = Year = Work Week
Pin assignment is for DualinLine Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D).
Device MC10186P MC10186FN Package PDIP16 PLCC20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / Rail*A clock is a clock transition from a low to a high state.
Characteristic Power Supply Drain Current Input Current
IinL Output Voltage Output Voltage Threshold Voltage Threshold Voltage Logic 1 Logic 0 Logic 1 Logic 0 VOH VOL VOHA VOLARise Time Fall Time Setup Time Hold Time
[ Output level to be measured after clock pulse.
IinL Output Voltage Output Voltage Threshold Voltage Threshold Voltage Switching Times Propagation Delay Logic 1 Logic 0 Logic 1 Logic 0 (50 Load) VOH VOL VOHA VOLARise Time Fall Time Setup Time Hold Time Toggle Frequency (Max)
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50ohm resistor to 2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.
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