Details, datasheet, quote on part number: MC10188FN
PartMC10188FN
CategoryLogic => Buffers/Drivers => Buffers
TitleBuffers
DescriptionHex Buffer With Enable , Package: Plcc, Pins=20
CompanyON Semiconductor
DatasheetDownload MC10188FN datasheet
Quote
Find where to buy
 
  

 

Features, Applications

The is a high­speed hex buffer with a common Enable input. When Enable is in the high state, all outputs are in the low state. When Enable is in the low state, the outputs take the same state as the inputs. Power Dissipation 180 mW typ/pkg (No Load) Propagation Delay 2.0 ns typ 2.5 ns typ ­ Q)

CDIP­16 L SUFFIX CASE PDIP­16 P SUFFIX CASE PLCC­20 FN SUFFIX CASE 775 10188 AWLYYWW MC10188P AWLYYWW

VCC1 AOUT BOUT COUT AIN BIN CIN VEE VCC2 FOUT EOUT DOUT FIN EIN DIN COMMON WW = Assembly Location = Wafer Lot = Year = Work Week

Device MC10188L MC10188P Package PDIP­16 PLCC­20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / Rail

Pin assignment is for Dual­in­Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D).

Characteristic Power Supply Drain Current Input Current

Output Voltage Output Voltage Threshold Voltage Threshold Voltage Switching Times Propagation Delay Rise/Fall Time

Logic 1 Logic 0 Logic 1 Logic 0 (50 Load) Enable Data to 80%)
TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VILmin VIHAmin VILAmax VEE
Logic 1 Logic 0 Logic 1 Logic 0 (50 Load) Enable Data to 80%)

Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50­ohm resistor to ­2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.

PLCC­20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775­02 ISSUE C

NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).


 

Related products with the same datasheet
MC10188P
Some Part number from the same manufacture ON Semiconductor
MC10188FNR2 Hex Buffer With Enable, Package: Plcc, Pins=20
MC10188P Hex Buffer With Enable , Package: Plcc, Pins=20
MC10189 Hex Inverter With Enable
MC10189FN Hex Inverter With Enable , Package: Plcc, Pins=20
MC10189FNR2 Hex Inverter With Enable, Package: Plcc, Pins=20
MC10189P Hex Inverter With Enable , Package: Plcc, Pins=20
MC10192 Quad Bus Driver
MC10192FN Quad Bus Driver , Package: Plcc, Pins=20
MC10192FNR2 Quad Bus Driver, Package: Plcc, Pins=20
MC10192P Quad Bus Driver , Package: Plcc, Pins=20
MC10195 Hex Inverter/buffer
MC10195L Hex Inverter/Buffer, Package: Cdip, Pins=16
MC10197 Hex And Gate
MC10197FNR2 Hex And Gate , Package: Plcc, Pins=20
MC10197L Hex And Gate, Package: Cdip, Pins=16
MC10197P Hex And Gate , Package: Plcc, Pins=20
MC10198 Monostable Multivibrator
MC10198FN Monostable Multivibrator , Package: Plcc, Pins=20
MC10198FNR2 Monostable Multivibrator, Package: Plcc, Pins=20
MC10216 High Speed Triple Line Receiver
MC10216FN High Speed Triple Line Receiver , Package: Plcc, Pins=20
Same catergory

74ABT16825A : 74ABT16825A; 74ABTH16825A; 18-bit Buffer/line Driver; Non-inverting (3-State);; Package: SOT364-1 (TSSOP56), SOT371-1 (SSOP56).

74LVC1G175 : Single D-type Flip-flop With Reset; Positive-edge Trigger.the 74LVC1G175 is a High-performance, Low-voltage, Si-gate CMOS Device, Superior to MOSt Advanced CMOS Compatible TTL Families. The Input CAN be Driven From Either 3.3 V or 5 V Devices. This Feature Allows The Use of This Device in a Mixed 3.3 V And 5 V Environment. This Device is Fully Specified.

CD54ACT74 : . CD54ACT74, CD74ACT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current ­ Fanout 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection.

CD74ACT04 : CMOS/BiCMOS->AC/ACT Family. Hex Inverters. Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current ­ Fanout 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015 The `ACT04 devices contain six independent inverters.

CD74HCT107 : CMOS/BiCMOS->HC/HCT Family. Dual J-k Flip-flop With Reset Negative-edge Trigger.

CTS191MS : Radiation Hardened Synchronous 4-bit Up/down Counter. 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T16 TOP VIEW 3 Micron Radiation Hardened CMOS SOS Total Dose 200K RAD (Si) SEP Effective LET No Upsets: >100 MEV-cm2/mg Single Event Upset (SEU) Immunity x 10-9 Errors/BitDay (Typ) Dose Rate Survivability: x 1012 RAD (Si)/s Dose Rate Upset: >1010 RAD (Si)/s 20ns Pulse Cosmic.

HD74SSTV16857B : for DIMM->HD74SSTV series. The a 14-bit registered buffer designed for 2.7 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input. Data flow from Q is controlled by differential clock pins (CLK, CLK) and the RESET. Data is triggered on the positive edge of the positive clock (CLK), and the negative clock (CLK) must be used to maintain noise margins.

HEF4724B : CMOS/BiCMOS->4000 Family. HEF4724B MSI; 8-bit Addressable Latch. For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family s HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC Product File under Integrated Circuits, IC04 January 1995 The an 8-bit addressable latch with three address inputs A2), a data input (D), an active LOW enable input (E), an active HIGH clear.

ICM7216B : Bipolar->ALS Family. 8-Digit, Multi-Function, Frequency Counters/timers.

IDT74FCT163AT : CMOS/BiCMOS->FCT/FCT-T Family. Fast CMOS Synchronous Presettable Binary Counter.

IDTQS3LR384 : Quickswitch(r) High-speed CMOS 10-bit Low Power, Low Resistance Bus Switch.

MM74HC139 : CMOS/BiCMOS->HC/HCT Family. Dual 2-to-4 Line Decoder. The MM74HC139 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications. It possesses the high noise immunity and low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky TTL logic. The MM74HC139 contain two independent one-of-four.

N74F50728D : Synchronizing Cascaded Dual Positive Edge-triggered D-type Flip-flop. 74F50728 Synchronizing cascaded dual positive edge-triggered D-type flip-flop Synchronizing cascaded dual positive edge-triggered D-type flip-flop Metastable immune characteristics Output skew less than 1.5ns See 74F5074 for synchronizing dual D-type flip-flop See 74F50109 for synchronizing dual J­K positive edge-triggered Clock triggering occurs at a voltage.

SN54HCT126 : CMOS/BiCMOS->HC/HCT Family. Quad Bus Buffer Gates With 3-state Outputs.

SN74LS08D : ti SN74LS08, Quadruple 2-Input Positive-and Gates. PRODUCTION DATA information is current as of publication date. Products conform to s per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. .

TC7SL04 : CMOS/BiCMOS->AC/ACT Family. CMOS Inverter.

CBTL03SB212BS : MULTIPLEXER, PQCC20. s: Package Type: 4 X 4 MM, 0.85 MM HEIGHT, PLASITC, MO-220, HVQFN-20 ; Number of Pins: 20.

933373460652 : POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16. s: Flip-Flop Type: D ; Triggering: Positive-edge Triggered ; Supply Voltage: 5V ; Output Characteristics: TRUE ; Propagation Delay: 155 ns ; fMAX: 20 MHz ; Package Type: PLASTIC, SOT-109-1, SO-16 ; Number of Pins: 16.

 
0-C     D-L     M-R     S-Z