Details, datasheet, quote on part number: MC10198FNR2
PartMC10198FNR2
CategoryLogic => Multivibrators/Oscillators
DescriptionMonostable Multivibrator, Package: Plcc, Pins=20
CompanyON Semiconductor
DatasheetDownload MC10198FNR2 datasheet
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Features, Applications

The is a retriggerable monostable multivibrator. Two enable inputs permit triggering on any combination of positive or negative edges as shown in the accompanying table. The trigger input is buffered by Schmitt triggers making it insensitive to input rise and fall times. The pulse width is controlled by an external capacitor and resistor. The resistor sets a current which is the linear discharge rate of the capacitor. Also, the pulse width can be controlled by an external current source or voltage (see applications information). For high­speed response with minimum delay, a hi­speed input is also provided. This input bypasses the internal Schmitt triggers and the output responds within 2 nanoseconds typically. Output logic and threshold levels are standard MECL 10,000. Test conditions are per Table 2. Each "Precondition" referred to in Table 2 is per the sequence of Table 415 mW typ/pkg (No Load) tpd 4.0 ns typ Trigger Input 2.0 ns typ Hi­Speed Input to Q Min Timing Pulse Width PWQmin ns typ1 Max Timing Pulse Width PWQmax ms typ2 Min Trigger Pulse Width PWT 2.0 ns typ Min Hi­Speed PWHS 3.0 ns typ Trigger Pulse Width Enable Setup Time tset 1.0 ns typ Enable Hold Time thold 1.0 ns typ 1 CExt = 0 (Pin 4 open), RExt = 0 (Pin 6 to VEE) 2 CExt = 10 mF, RExt 2.7 kW

CDIP­16 L SUFFIX CASE PDIP­16 P SUFFIX CASE PLCC­20 FN SUFFIX CASE 775 10198 AWLYYWW MC10198P AWLYYWW MC10198L AWLYYWW

= Assembly Location = Wafer Lot = Year = Work Week

Device MC10198P MC10198FN Package PDIP­16 PLCC­20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / Rail

6 REXT E pos EXTERNAL PULSE WIDTH CONTROL ENEG TRIGGER INPUT HI-SPEED INPUT
Q CEXT EPOS REXT EXT.PULSE WIDTH CONTROL

INPUT EPos ENeg Triggers on both positive & negative input slopes Triggers on positive input slope Triggers on negative input slope Trigger is disabled OUTPUT

Pin assignment is for Dual­in­Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D).

a.) b.) c.) = 0 Apply VIHmax to Pin 5 and 10. Apply VILmin to Pin 15. Ground Pin 4. a.) Open Pin 1. b.) Apply ­3.0 Vdc to Pin 4. Hold these conditions for w10 ns. 3. Return Pin 4 to Ground and perform test as indicated in Table 2.

TABLE 2 CONDITIONS FOR TESTING OUTPUT LEVELS (See Table 1 for Precondition Sequence)

Pin Conditions Test P.U.T. 10 13 VIL min P1 VIL min P1 VILA max VIHA min VIL min P2 P3 VIH max VIH max VIH max VIH max P1 15 Test P.U.T. 5

Pin Conditions 10 VIHA min VILA max 13 P1 VILA max VIHA min VIL min VIL min P2 P3 VIH max VIH max VIHA min VILA max VIH max VIH max VIH max VIH max VIHA min VILA max P1 15

Precondition VOH 2 VOH 3 Precondition VOL 3 VOL 2 Precondition VOHA 2 VOHA 3 Precondition VOHA 2 VOHA 3 Precondition VOHA 2 VOHA 3 Precondition VOHA 2 VOHA 3 Precondition VOHA 2 VOHA 3

Precondition VOHA 2 VOHA 3 Precondition VOLA 3 VOLA 2 Precondition VOLA 2 VOLA 3 Precondition VOLA 3 VOLA 2 Precondition VOLA 3 VOLA 2 Precondition VOLA 3 VOLA 2 Precondition VOLA 3 VOLA 2


 

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