|Category||Logic => Flip-Flops|
|Description||High Speed Dual Type D-type Master-slave Flip-Flop, Package: Plcc, Pins=20|
|Datasheet||Download MC10231FNR2 datasheet
|MC10231 High Speed Dual Type D Master-Slave Flip-Flop
The is a dual masterslave type D flipflop. Asynchronous Set (S) and Reset (R) override Clock (CC) and Clock Enable (CE) inputs. Each flipflop may be clocked separately by holding the common clock in the low state and using the enable inputs for the clocking function. If the common clock to be used to clock the flipflop, the Clock Enable inputs must be in the low state. In this case, the enable inputs perform the function of controlling the common clock. The output states of the flipflop change on the positive transition of the clock. A change in the information present at the data (D) input will not affect the output information at any other time due to masterslave construction. 270 mW typ/pkg (No Load) tpd 2 ns typ tTog = 225 MHz typ tr, 2.0 ns typ (20%80%)
CDIP16 L SUFFIX CASE PDIP16 P SUFFIX CASE PLCC20 FN SUFFIX CASE 775 10231 AWLYYWW MC10231P AWLYYWW MC10231L AWLYYWW= Assembly Location = Wafer Lot = Year = Work Week
CE + CC. A clock is a clock transition from a low to a high state.
Pin assignment is for DualinLine Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D).
Device MC10231P MC10231FN Package PDIP16 PLCC20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / RailCharacteristic Power Supply Drain Current Input Current
IinL Output Voltage Output Voltage Threshold Voltage Threshold Voltage Logic 1 Logic 0 Logic 1 Logic 0 VOH VOL VOHA VOLASetup Time Hold Time Toggle Frequency (Max)
* Individually test each input; apply VILmin to pin under test. [ Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)
IinL Output Voltage Output Voltage Threshold Voltage Threshold Voltage Switching Times Clock Input Logic 1 Logic 0 Logic 1 Logic 0 (50 Load) VOH VOL VOHA VOLA
* Individually test each input applying IH or VIL to input under test. [ Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50ohm resistor to 2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.
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