|Description||Positive J-k Positive Edge-triggered Flip-flops|
|Company||Philips Semiconductors (Acquired by NXP)|
|Datasheet||Download I74F109N datasheet
|Cross ref.||Similar parts: JM38510/34102BEA, CD54ACT109, CD54HCT109, CD74ACT109, CD74HCT109, SN54ALS109A, SN54LS109A, SN74ALS109A, SN74LS109A, 74F109PC|
The is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock (CP) input. The J and K are edge-triggered inputs which control the state changes of the flip-flops as described in the function table. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. The J and K inputs must be stable just one setup time prior to the low-to-high transition of the clock for predictable operation. The JK design allows operation a D flip-flop by tying J and K inputs together. Although the clock input is level sensitive, the positive transition of the clock pulse between the 0.8V and 2.0V levels should be equal to or less than the clock to output delay time for reliable operation. TYPE 74F109 TYPICAL fmax 125MHz TYPICAL SUPPLY CURRENT (TOTAL) 12.3mA
ORDER CODE DESCRIPTION 16-pin plastic DIP 16-pin plastic SO COMMERCIAL RANGE VCC 5V ±10%, Tamb N74F109N N74F109D INDUSTRIAL RANGE VCC 5V ±10%, Tamb I74F109N I74F109D PKG DWG SOT38-4 SOT109-1
PINS Q1 J inputs K inputs Clock inputs (active rising edge) Set inputs (active Low) Reset inputs (active Low) Data outputs DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW 20µA/1.8mA 1.0mA/20mANOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
INPUTS OUTPUTS OPERATING MODE Asynchronous set Asynchronous reset Undetermined* Hold Toggle Load "1" (set) Load "0" (reset) Hold 'no change" CP X
NOTES: H = High-voltage level h = High-voltage level one setup time prior to low-to-high clock transition L = Low-voltage level l = Low-voltage level one setup time prior to low-to-high clock transition q = Lower case indicate the state of the referenced output prior to the low-to-high clock transition X = Don't care = Low-to-high clock transition = Not low-to-high clock transition * = Both outputs will be high if both SD and RD go low simultaneously
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Commercial range Operating free-air free air temperature range Industrial range Storage temperature range to +150 PARAMETER RATING 0.5 to VCC to +70 UNIT mA °C
LIMITS SYMBOL VCC VIN VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Commercial range Operating free-air free air temperature range Industrial range 0 40 PARAMETER MIN NOM 5.0 MAX mA °C UNIT
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