Details, datasheet, quote on part number: I74F112N
CategoryLogic => Flip-Flops
Description74F112; Dual J-k Negative Edge-triggered Flip-flop;; Package: SOT109 (SO16)
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload I74F112N datasheet
Cross ref.Similar parts: SN74F112N, CD54ACT112, CD54HCT112, CD74HCT112, SN54ALS112A, SN54LS112A, SN54LS76A, SN74ALS112A, SN74LS112A, SN74S112A
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Features, Applications


The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level at the other inputs. A High level on the clock (CPn) input enables the J and K inputs and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CPn is High and flip-flop will perform according to the Function Table as long as minimum setup and hold times are observed. Output changes are initiated by the High-to-Low transition of the CPn. TYPE 74F112 TYPICAL PROPAGATION DELAY 100MHz

ORDER CODE DESCRIPTION 16-pin plastic DIP 16-pin plastic SO COMMERCIAL RANGE VCC 5V 10%, Tamb N74F112N N74F112D INDUSTRIAL RANGE VCC 5V 10%, Tamb I74F112N I74F112D PKG DWG SOT38-4 SOT109-1

PINS Q1 J inputs K inputs Set inputs (active Low) Reset inputs (active Low) Clock Pulse input (active falling edge) Data outputs DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW 20A/2.4mA 1.0mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20A in the High state and 0.6mA in the Low state.

INPUTS RD CP OUTPUTS L H* Asynchronous Set Asynchronous Reset Undetermined * Toggle Load "0" (Reset) Load "1" (Set) Hold "no change" Hold "no change" OPERATING MODE

H = High voltage level h = High voltage level one setup time prior to High-to-Low clock transition L = Low voltage level l = Low voltage level one setup time prior to High-to-Low clock transition q = Lower case letters indicate the state of the reference output prior to the High-to-Low clock transition X = Don't care = High-to-Low clock transition * = Both outputs will be High while both SD and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously.


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