Details, datasheet, quote on part number: I74F113N
PartI74F113N
CategoryLogic => Flip-Flops
Description74F113; Dual J-k Negative Edge-triggered Flip-flops Without Reset;; Package: SOT27-1 (DIP14)
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload I74F113N datasheet
Cross ref.Similar parts: CD74HCT107, CD74HCT73, SN54LS73A
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Features, Applications

74F113 Dual J-K negative edge-triggered flip-flops without reset
Dual J-K negative edge-triggered flip-flops without reset
FEATURE
DESCRIPTION

The 74F113, dual negative edge-triggered JK-type flip-flop, features individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. The asynchronous SD input, when low, forces the outputs to the steady state levels as shown in the function table regardless of the level at the other inputs. A high level on the clock (CP) input enables the J and K inputs and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CP is high and flip-flop will perform according to the function table as long as minimum setup and hold times are observed. Output changes are initiated by the high-to-low transition of the CP. TYPE 74F113 TYPICAL fmax 100MHz

ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC 5V ±10%, Tamb N74F113N N74F113D INDUSTRIAL RANGE VCC 5V ±10%, Tamb I74F113N I74F113D PKG. DWG. #

PINS Q1 J inputs K inputs Clock inputs (active falling edge) Set inputs (active low) Data outputs DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW 20µA/3.0mA 1.0mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.

INPUTS SD CP OUTPUTS OPERATING MODE Asynchronous set Toggle Load "1" (set) Load "0" (reset) Hold 'no change"

NOTES: H = High-voltage level h = High-voltage level one setup time prior to high-to-low clock transition L = Low-voltage level l = Low-voltage level one setup time prior to high-to-low clock transition q = Lower case indicate the state of the referenced output prior to the high-to-low clock transition X = Don't care = high-to-low clock transition

(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Commercial range free air temperature range Operating free-air Storage temperature range Industrial range PARAMETER RATING ­0.5 to VCC to +150 UNIT mA °C

LIMITS SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Commercial range Operating free-air free air temperature range Industrial range 0 ­40 PARAMETER MIN NOM 5.0 MAX 5.5 UNIT mA °C


 

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