|Description||4-bit Binary Counter|
|Company||Philips Semiconductors (Acquired by NXP)|
|Datasheet||Download I74F161AD datasheet
|Cross ref.||Similar parts: SN74F161AD, CD74ACT163, SN74F163A, CD74ACT161, CD74HCT161, CD74HCT163, SN74ALS161B, SN74ALS163B, SN74AS163, SN74LS161A|
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
Synchronous counting and loading Two count enable inputs for n-bit cascading Positive edge-triggered clock Asynchronous Master Reset (74F161A) Synchronous Reset (74F163A) High speed synchronous expansion Typical count rate of 130MHz Industrial range to +85°C) availableDESCRIPTION
4-bit binary counters feature an internal carry look-ahead and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock. The clock input is buffered. The outputs of the counters may be preset to High or Low level. A Low level at the Parallel Enable (PE) input disables the counting action and causes the data at the D0D3 inputs to be loaded into the counter on the positive-going edge of the clock (provided that the setup and hold requirements for PE are met). Preset takes place regardless of the levels at Count Enable (CEP, CET) inputs.
A Low level at the Master Reset (MR) input sets all the four outputs of the flip-flops 74F161A to Low levels, regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function). For the 74F163A, the clear function is synchronous. A Low level at the Synchronous Reset (SR) input sets all four outputs of the flip-flops Q3) to Low levels after the next positive-going transition on the clock (CP) input (provided that the setup and hold time requirements for SR are met). This action occurs regardless of the levels at PE, CET, and CEP inputs. The synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate (see Figure 1). The carry look-ahead simplifies serial cascading of the counters. Both Count Enable (CEP and CET) inputs must be High to count. The CET input is fed forward to enable the TC output. The TC output thus enabled will produce a High output pulse of a duration approximately equal to the High level output of Q0. This pulse can be used to enable the next cascaded stage (see Figure 2). The TC output is subjected to decoding spikes due to internal race conditions. Therefore, it is not recommended for use as clock or asynchronous reset for flip-flops, registers, or counters.
ORDER CODE DESCRIPTION 16-pin plastic DIP 16-pin plastic SO COMMERCIAL RANGE VCC 5V ±10%, Tamb N74F161AD, N74F163AD INDUSTRIAL RANGE VCC 5V ±10%, Tamb I74F161AD, I74F163AD DRAWING NUMBER SOT38-4 SOT109-1
PINS D3 CEP CET Q3 DESCRIPTION Data inputs Count Enable Parallel input Count Enable Trickle input Clock input (active rising edge) Parallel Enable input (active Low) Asynchronous Master Reset input (active Low) for 74F161A Synchronous Reset input (active Low) for 74F163A Terminal count output Flip-flop outputs 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW 20µA/0.6mA 1.0mA/20mANOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
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