Details, datasheet, quote on part number: I74F50728D
PartI74F50728D
CategoryLogic => Flip-Flops
Description74F50728; Synchronizing Cascaded Dual Positive Edge-triggered D-type Flip-flop;; Package: SOT108-1 (SO14), SOT27-1 (DIP14)
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload I74F50728D datasheet
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Features, Applications

74F50728 Synchronizing cascaded dual positive edge-triggered D-type flip-flop
Synchronizing cascaded dual positive edge-triggered D-type flip-flop
FEATURES

Metastable immune characteristics Output skew less than 1.5ns See 74F5074 for synchronizing dual D-type flip-flop See 74F50109 for synchronizing dual J­K positive edge-triggered

Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive­going pulse. Following the hold time interval, data at the Dn input may be changed without affecting the levels of the output. Data entering the 74F50728 requires two clock cycles to arrive at the outputs. The 74F50728 is designed so that the outputs can never display a metastable state due to setup and hold time violations. If setup time and hold time are violated the propagation delays may be extended beyond the specifications but the outputs will not glitch or display a metastable state. Typical metastability parameters for the 74F50728 are: 135ps and X 106 sec where represents a function of the rate at which a latch in a metastable state resolves that condition and To represents a function of the measurement of the propensity of a latch to enter a metastable state. TYPICAL SUPPLY CURRENT (TOTAL) 23mA

for synchronizing dual D-type flip-flop with edge-triggered set and reset
DESCRIPTION

The is a cascaded dual positive edge­triggered D­type featuring individual data, clock, set and reset inputs; also true and complementary outputs. Set (SDn) and reset (RDn) are asynchronous active low inputs and operate independently of the clock (CPn) input. They set and reset both flip­flops of a cascaded pair simultaneously. Data must be stable just one setup time prior to the low­to­high transition of the clock for guaranteed propagation delays.

ORDER CODE COMMERCIAL RANGE DESCRIPTION Tamb +70°C 14­pin plastic DIP 14­pin plastic N74F50728N N74F50728D VCC 5V ±10%, INDUSTRIAL RANGE Tamb SOT27-1 SOT108-1 VCC 5V ±10%, PKG DWG #

PINS RD0, RD1 Data inputs Clock inputs (active rising edge) Set inputs (active low) Reset inputs (active low) DESCRIPTION 74F (U.L.) HIGH/ LOW LOAD VALUE HIGH/ LOW 20µA/20µA 1.0mA/20mA

Q0, Q1 Data outputs NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.

NOTE: Data entering the flip­flop requires two clock cycles to arrive at the output.

Synchronizing incoming signals to a system clock has proven to be costly, either in terms of time delays or hardware. The reason for this is that in order to synchronize the signals a flip­flop must be used to "capture" the incoming signal. While this is perhaps the only way to synchronize a signal, to this point, there have been problems with this method. Whenever the flop's setup or hold times are violated the flop can enter a metastable state causing the outputs in turn to glitch, oscillate, enter an intermediate state or change state in some abnormal fashion. Any of these conditions could be responsible for causing a system crash. To minimize this risk, flip­flops are often cascaded so that the input signal is captured on the first clock pulse and released on the second clock pulse (see Fig.1). This gives the first flop about one clock period minus the flop delay and minus the second flop's clock­to­Q setup time to resolve any metastable condition. This method greatly reduces the probability of the outputs of the synchronizing device displaying an abnormal state but the trade-off is that one clock cycle is lost to synchronize the incoming data and two separate flip­flops are required to produce the cascaded flop circuit. In order to assist the designer of synchronizing circuits Philips Semiconductors is offering the 74F50728.

The 50728 consists of two pair of cascaded D­type flip­flops with metastable immune features and is pin compatible with the 74F74. Because the flops are cascaded on a single part the metastability


 

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I74F50728N
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