|Category||Interface and Interconnect|
|Description||Octal Transceiver With 8-bit Parit Generator/checker|
|Company||Philips Semiconductors (Acquired by NXP)|
|Datasheet||Download I74F657N datasheet
|Cross ref.||Similar parts: SN74F657, CY54FCT543T, CY54FCT646T, SN54ABT2952A, SN54ABT543A, SN54ABT646A, SN54ABT652A, SN54ABT8245, SN54ALS646, SN54ALS652|
Combines 74F245 and 74F280A functions in one package High impedance base input for reduced loading (70µA in
high and low states) Ideal in applications where high output drive and light bus loading are required (IIL 70µA vs FAST std 600µA) 3state buffer outputs sink 64mA and source 15mA
The parity select (ODD/EVEN) input gives the user the option of odd or even parity systems. The parity (PARITY) pin is an output from the generator/checker when transmitting from the port to B (T/R = high) and an input when receiving from port to A port ( T/R = low). When transmitting (T/R = high) the parity select (ODD/EVEN) input is set, then the A port data is polled to determined the number of high bits. The parity (PARITY) output then goes to the logic state determined by the parity select (ODD/EVEN) setting and by the number of high bits on port A. For example, if the parity select (ODD/EVEN) is set low (even parity), and the number of high bits on port A is odd, then the parity (PARITY) output will be high, transmitting even parity. If the number of high bits on port A is even, then the parity (PARITY) output will be low, keeping even parity. When in receive mode (T/R = low) the B port is polled to determine the number of high bits. If parity select (ODD/EVEN) is low (even parity) and the number of highs on port B is: (1) odd and the parity (PARITY) input is high, then ERROR will be high, significantly no error. (2) even and the parity (PARITY) input is high, then ERROR will be asserted low, indicating an error. TYPE 74F657 TYPICAL PROPAGATION DELAY 8.0ns TYPICAL SUPPLY CURRENT( TOTAL) 100mA
Input diodes for termination effects 24pin plastic slim DIP (300mil) package Industrial temperature range available to +85°C)DESCRIPTION
The is an octal transceiver featuring noninverting buffers with 3state outputs and an 8bit parity generator/checker, and is intended for busoriented applications. The buffers have a guaranteed current sinking capability 24mA at the A ports and 64mA at the B ports. The transmit/receive (T/R) input determines the direction of the data flow through the bidirectional transceivers. Transmit (active high) enables data from A ports to B ports; receive (active low) enables data from B ports to A ports.
The output enable (OE) input disables both the A and B ports by placing them in a high impedance condition when the OE input is high.
ORDER CODE COMMERCIAL RANGE DESCRIPTION Tamb +70°C 24pin plastic slim DIP (300mil) 24pin plastic SOL 24pin plastic SSOP N74F657D N74F657DB VCC 5V ±10%, INDUSTRIAL RANGE Tamb SOT137-1 SOT340-1 VCC 5V ±10%, PKG DWG #
PINS B7 PARITY T/R ODD/EVEN B7 PARITY ERROR DESCRIPTION A ports 3state inputs B ports 3state inputs Parity input Transmit/receive input Parity select input Output enable input (active low) A ports 3state outputs B ports 3state outputs Parity output Error output 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW 3.0mA/24mA 15mA/64mA
Note to input and output loading and fan out table 1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. 90 July
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