Details, datasheet, quote on part number: I74F786D
Description4-bit Asynchronous Bus Arbiter
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload I74F786D datasheet
Find where to buy


Features, Applications


Arbitrates between 4 asynchronous inputs Separate grant output for each input Common output enable On board 4 input AND gate Metastable­free outputs Industrial temperature range available to +85°C)


The is an asynchronous 4­bit arbiter designed for high speed real­time applications. The priority of arbitration is determined on a first­come first­served basis. Separate bus grant (BGn) outputs are available to indicate which one of the request inputs is served by the arbitration logic. All BGn outputs are enabled by a common enable (EN) pin. In order to generate a bus request signal a separate 4 input AND gate is provided which may also be used as an independent AND gate. Unused bus request (BR) inputs may be disabled by tying them high.

The 74F786 is designed so that contention between two or more request signals will not glitch or display a metastable condition. In this situation an increase in the BRn to BGn tPHL may be observed. A typical 74F786 has = 0.41ns and = 5µsec. Where: h = Typical propagation delay through the device and t and To are device parameters derived from test results and can most nearly be defined as: = A function of the rate at which a latch in a metastable state resolves that condition. = A function of the measurement of the propensity of a latch to enter a metastable state. To is also a very strong function of the normal propagation delay of the device. For further information, please refer to the 74F786 application notes. TYPICAL SUPPLY CURRENT (TOTAL) 55mA

ORDER CODE DESCRIPTION 16­pin plastic DIP 16­pin plastic SO COMMERCIAL RANGE VCC 5V ±10%, Tamb N74F786N N74F786D INDUSTRIAL RANGE VCC 5V ±10%, Tamb I74F786N I74F786D PKG DWG # SOT 38-4 SOT109-1

PINS D EN YOUT ­ BG3 DESCRIPTION Bus request inputs (active low) AND gate inputs Common bus grant output enable input (active low) AND gate output Bus grant outputs (active low) 74F (U.L.) HIGH/ LOW LOAD VALUE HIGH/ LOW 20µA/0.6mA 3.0mA/24mA

NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.

The BRn inputs have no inherent priority. The arbiter assigns priority to the incoming requests as they are received, therefore, the first BR asserted will have the highest priority. When a bus request is received its corresponding bus grant becomes active, provided that EN is low. If additional bus requests are made during this time they are queued. When the first request is removed, the arbiter services the bus request with the next highest priority. Removing a request while a previous request is being serviced can cause a grant to be changed when arbitrating between three or four requests. For that reason, the user should not remove ungranted requests when arbitrating between three or four requests. This does not apply to arbitration between two requests. If two or more BRn inputs are asserted at precisely the same time, one of them will be selected at random, and all BGn outputs will be held in the high state until the selection is made. This guarantees that an erroneous BGn will not be generated even though a metastable condition may occur internal to the device. When the is in the high state the BGn outputs are forced high.

SYMBOL ­ BG3 YOUT GND VCC PINS TYPE Input Output Ground Power NAME Bus request inputs (active low) Inputs of the 4­input AND gate Enable input Bus grant outputs (active low) Output of the 4­input AND gate ground (0V) Positive supply voltages When low it enables the ­ BG3 outputs. These outputs indicate the selected bus request. BG0 corresponds to BR1, etc. FUNCTION The logic of this device arbitrates between these four inputs. Unused inputs should be tied high.


Related products with the same datasheet
Some Part number from the same manufacture Philips Semiconductors (Acquired by NXP)
I74F786N 4-bit Asynchronous Bus Arbiter
I74F823D Bus Interface Registers
I74F86D 74F86; Quad 2-input Exclusive-OR GATE;; Package: SOT108-1 (SO14), SOT27-1 (DIP14)
I74F86N Quad 2-input Exclusive-OR GATE
ICM7555 ICM7555; General Purpose CMOS Timer
IRF530N IRF530N; N-channel Trenchmos (tm) Transistor;; Package: SOT78 (TO-220AB, SC-46)
IRF540 IRF540; IRF540S; N-channel Trenchmos (tm) Transistor;; Package: SOT78 (TO-220AB, SC-46)
IRF630 IRF630; IRF630S; N-channel Trenchmos (tm) Transistor;; Package: SOT78 (TO-220AB, SC-46)
IRF640 IRF640; IRF640S; N-channel Trenchmos (tm) Transistor;; Package: SOT78 (TO-220AB, SC-46)
IRF730 IRF730; Powermos Transistors Avalanche Energy Rated
IRF830 IRF830; Powermos Transistor Avalanche Energy Rated
IRF840 IRF840; Powermos Transistor Avalanche Energy Rated
IRFP450 Powermos Transistors Avalanche Energy Rated: 500v, 14a
IRFP460 Powermos Transistors Avalanche Energy Rated: 500v, 20a
IRFR220 IRFR220; N-channel Enhancement Mode Field Effect Transistor;; Package: SOT428 (SC-63, D-PAK)
IRFZ24N IRFZ24N; N-channel Enhancement Mode Trenchmos (tm) Transistor;; Package: SOT78 (TO-220AB, SC-46)
IRFZ44N IRFZ44N; N-channel Enhancement Mode Trenchmos (tm) Transistor;; Package: SOT78 (TO-220AB, SC-46)
IRFZ44NS IRFZ44NS; N-channel Enhancement Mode Trenchmos (tm) Transistor
IRFZ48N IRFZ48N; N-channel Enhancement Mode Trenchmos (tm) Transistor;; Package: SOT78 (TO-220AB, SC-46)
IRLZ34N IRLZ34N; N-channel Enhancement Mode Logic Level Trenchmos (tm) Transistor;; Package: SOT78 (TO-220AB, SC-46)

BT136XSERIESD : BT136X Series; Triacs

BZD23-C75TR :

BZX79-A10 : BZX79 Series; Voltage Regulator Diodes

HEF40245BF : Octal Bus Transceiver With 3-state Outputs

PDTA124ES : SOT/Surface Mount PNP Resistor-equipped Transistor

PDTA143X : PDIUSBP11A; Universal Serial Bus Transceiver;; Package: SOT108-1 (SO14), SOT337-1 (SSOP14), SOT402-1 (TSSOP14)

TDA9817T : TDA9817; TDA9818; Single/multistandard Vif/sif-pll And Fm-pll/am Demodulators;; Package: SOT137 (SO24), SOT340-1 (SSOP24)

BAP55L : Silicon PIN diode Planar PIN diode in a SOD882 leadless ultra small plastic SMD package. Features High speed switching for RF signals Very low series inductance Low diode capacitance For applications up to 3 GHz Low forward resistance

Same catergory

74AC16472DL : Registered Transceivers. ti 74AC16472, 18-Bit Registered Transceivers With 3-State Outputs.

74HC27 : 74HC/HCT27; Triple 3-input NOR GATE;; Package: SOT108-1 (SO14), SOT27-1 (DIP14), SOT337-1 (SSOP14), SOT402-1 (TSSOP14).

74LCXHR162245 : LCX->Low Voltage HCMOS, 5V I/O Tolerant. Low Voltage CMOS 16-BIT Bus Transceiver (3-STATE) With 5V Tolerant Inputs And Outputs.

74LVCH16702A : 3.3V CMOS 18-BIT Read/write Buffer With 5V Tolerant I/o And Bus-hold. 3.3V CMOS 18-BIT READ/WRITE BUFFER WITH 5 VOLT TOLERANT I/O Typical tSK(o) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method > 200V using machine model = 0) VCC ± 0.3V, Normal Range VCC to 3.6V, Extended Range CMOS power levels (0.4µ W typ. static) All inputs, outputs, and I/O are 5V tolerant Supports hot insertion Available in SSOP,.

7705701RA : Inverting Buffers and Drivers. ti SN54LS244, Octal Buffers And Line Drivers With 3-State Outputs.

CD74FCT841A : CMOS/BiCMOS->FCT/FCT-T Family. Bicmos 10-bit Bus-interface D-type Latch With 3-state Outputs.

CD74HCT193E : ti CD74HCT193, High Speed CMOS Logic Presettable Synchronous 4-Bit Binary Up/down Counters With Asynchronous Reset.

CD74HCT73E : ti CD74HCT73, High Speed CMOS Logic Dual Negative-edge-triggered J-k Flip-flops With Reset.

DM74S158 : Multiplexers->Bipolar->S Family. Quad 2-to-1 Line Data Selector/multiplexer (Inverting).

MC100E167FN : Multiplexers. 5V Ecl 6-Bit 2:1 Mux-register , Package: Plcc, Pins=28. The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop outputs by a positive edge or CLK2 (or both). A HIGH on the Master Reset (MR) pin asynchronously forces all Q outputs LOW. The 100 Series contains temperature.

MC74F620DW : Octal Bus Transceiver With 3-state Outputs ( Inverting And Noninverting ).

MC74HC244ADT : Buffers. Octal Buffer , Package: Tssop, Pins=20. MC74HC244A Octal 3-State Noninverting Buffer/Line Driver/ Line Receiver The MC74HC244A is identical in pinout to the LS244. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This octal noninverting buffer/line driver/line receiver is designed to be used with 3­state memory address.

MC74VHC138DT : Multiplexers. Decoder/Demultiplexer, Package: Tssop, Pins=16. The is an advanced high speed CMOS 3­to­8 decoder fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. When the device is enabled, three Binary Select inputs ­ A2) determine which one of the outputs ­ Y7) will go Low. When enable input.

SN54ALS648 : Bus Oriented Circuits. Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data Choice of True or Inverting Data Paths Choice 3-State or Open-Collector Outputs Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs DEVICE OUTPUT 3 state 3 state LOGIC True Inverting.

SN74ABT841A : CMOS/BiCMOS->ABT/BCT Family. 10-bit Bus-interface D-type Latch With 3-state Outputs.

SN74AHC374 : CMOS/BiCMOS->HC/HCT Family. Octal Edge-triggered D-type Flip-flops With 3-state Outputs.

SN74LS352D : Dual 4-input Multiplexer. The is a very high-speed Dual 4-input Multiplexer with Common Select inputs and individual Enable inputs for each section. It can select two bits of data from four sources. The two buffered outputs present data in the inverted (complementary) form. The 74LS352 is the functional equivalent of the SN54/ 74LS153 except with inverted outputs. Inverted Version.

SN74LVCH32245A : Bus Oriented Circuits. 32-bit Bus Transceiver With 3-state Outputs. Member of the Texas Instruments Widebus+ Family Operates From 3.6 V Inputs Accept Voltages 5.5 V Max tpd 3.3 V Typical VOLP (Output Ground Bounce) V at VCC = 25°C Typical VOHV (Output VOH Undershoot) V at VCC = 25°C Ioff Supports Partial-Power-Down Mode Operation Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V.

SN74LVT16952 : Bus Oriented Circuits. 3.3v Abt 16-bit Registered Transceiver With 3-state Outputs.

TC7SP332WBG : P SERIES, 2-INPUT OR GATE, PBGA6. s: Gate Type: OR ; Supply Voltage: 1.2V ; Logic Family: CMOS ; Inputs: 2 ; Propagation Delay: 37 ns ; Operating Temperature: -40 to 85 C (-40 to 185 F) ; Pin Count: 6 ; IC Package Type: Other, 1 X 2 MM, 0.40 MM PITCH, WFBGA-6.

0-C     D-L     M-R     S-Z