Details, datasheet, quote on part number: I74F786D
PartI74F786D
CategoryLogic
Description4-bit Asynchronous Bus Arbiter
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload I74F786D datasheet
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Features, Applications

FEATURES

Arbitrates between 4 asynchronous inputs Separate grant output for each input Common output enable On board 4 input AND gate Metastable­free outputs Industrial temperature range available to +85°C)

DESCRIPTION

The is an asynchronous 4­bit arbiter designed for high speed real­time applications. The priority of arbitration is determined on a first­come first­served basis. Separate bus grant (BGn) outputs are available to indicate which one of the request inputs is served by the arbitration logic. All BGn outputs are enabled by a common enable (EN) pin. In order to generate a bus request signal a separate 4 input AND gate is provided which may also be used as an independent AND gate. Unused bus request (BR) inputs may be disabled by tying them high.

The 74F786 is designed so that contention between two or more request signals will not glitch or display a metastable condition. In this situation an increase in the BRn to BGn tPHL may be observed. A typical 74F786 has = 0.41ns and = 5µsec. Where: h = Typical propagation delay through the device and t and To are device parameters derived from test results and can most nearly be defined as: = A function of the rate at which a latch in a metastable state resolves that condition. = A function of the measurement of the propensity of a latch to enter a metastable state. To is also a very strong function of the normal propagation delay of the device. For further information, please refer to the 74F786 application notes. TYPICAL SUPPLY CURRENT (TOTAL) 55mA

ORDER CODE DESCRIPTION 16­pin plastic DIP 16­pin plastic SO COMMERCIAL RANGE VCC 5V ±10%, Tamb N74F786N N74F786D INDUSTRIAL RANGE VCC 5V ±10%, Tamb I74F786N I74F786D PKG DWG # SOT 38-4 SOT109-1

PINS D EN YOUT ­ BG3 DESCRIPTION Bus request inputs (active low) AND gate inputs Common bus grant output enable input (active low) AND gate output Bus grant outputs (active low) 74F (U.L.) HIGH/ LOW LOAD VALUE HIGH/ LOW 20µA/0.6mA 3.0mA/24mA

NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.

The BRn inputs have no inherent priority. The arbiter assigns priority to the incoming requests as they are received, therefore, the first BR asserted will have the highest priority. When a bus request is received its corresponding bus grant becomes active, provided that EN is low. If additional bus requests are made during this time they are queued. When the first request is removed, the arbiter services the bus request with the next highest priority. Removing a request while a previous request is being serviced can cause a grant to be changed when arbitrating between three or four requests. For that reason, the user should not remove ungranted requests when arbitrating between three or four requests. This does not apply to arbitration between two requests. If two or more BRn inputs are asserted at precisely the same time, one of them will be selected at random, and all BGn outputs will be held in the high state until the selection is made. This guarantees that an erroneous BGn will not be generated even though a metastable condition may occur internal to the device. When the is in the high state the BGn outputs are forced high.

SYMBOL ­ BG3 YOUT GND VCC PINS TYPE Input Output Ground Power NAME Bus request inputs (active low) Inputs of the 4­input AND gate Enable input Bus grant outputs (active low) Output of the 4­input AND gate ground (0V) Positive supply voltages When low it enables the ­ BG3 outputs. These outputs indicate the selected bus request. BG0 corresponds to BR1, etc. FUNCTION The logic of this device arbitrates between these four inputs. Unused inputs should be tied high.


 

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