|Description||Dual Forward-conducting P-gate Thyristors Programmable Overvoltage Protectors|
|Datasheet||Download TISP61511D datasheet
|Cross ref.||Similar parts: TPD13S523, TPD2E001|
TISP61511D, TISP61512P DUAL FORWARD-CONDUCTING P-GATE THYRISTORS PROGRAMMABLE OVERVOLTAGE PROTECTORS
Dual Voltage-Programmable Protectors. - Wide -80 V Programming Range - Low 5 mA max. Triggering Current - High 150 mA min. Holding Current Rated for International Surge Wave Shapes
- No internal connection Terminal typical application names shown in parenthesis '61512P PACKAGE (TOP VIEW)
DEVICE TYPE MGSS150-2 8-pin Plastic DIP TISP61512P 8-pin Small-Outline PACKAGE TYPE FUNCTIONAL REPLACEMENT TISP61511D or order as TISP61511DR for Taped and Reeled- No internal connection Terminal typical application names shown in parenthesis
The TISP61511D and TISP61512P are dual forward-conducting buffered p-gate overvoltage protectors. They are designed to protect monolithic Subscriber Line Interface Circuits, SLICs, against overvoltages on the telephone line caused by lightning, ac power contact and induction. The TISP61511D and TISP61512P limit voltages that exceed the SLIC supply rail voltage.
Terminals K1, K2 and A correspond to the alternative line designators T, R and A, B and C. The negative protection voltage is controlled by the voltage, VGG, applied to the G terminal.
The SLIC line driver section is typically powered from 0 V (ground) and a negative voltage in the region -70 V. The protector gate is connected to this negative supply. This references the protection (clipping) voltage to the negative supply voltage. As the protection voltage will track the negative supply voltage the overvoltage stress on the SLIC is minimised. Positive overvoltages are clipped to ground by diode forward conduction. Negative overvoltages are initially clipped close to the SLIC negative supply rail value. If sufficient current is available from the overvoltage, then the protector will crowbar into a low voltage on-state condition. As the current subsides the high holding current of the crowbar prevents d.c. latchup. These monolithic protection devices are fabricated in ion-implanted planar vertical power structures for high reliability and in normal system operation they are virtually transparent. The buffered gate design reduces the loading on the SLIC supply during overvoltages caused by power cross and induction.
Information is current as of publication date. Products conform to specifications in accordance with the terms of Power Innovations standard warranty. Production processing does not necessarily include testing of all parameters.
RATING Repetitive peak off-state voltage, TJ 85°C Repetitive peak gate-cathode voltage, TJ 85°C Non-repetitive peak on-state pulse current (see Notes 1 and 2/10 µs Non-repetitive peak on-state current, 50 Hz (see Notes 1 and 2) full-sine-wave, ms 1s Non-repetitive peak gate current, half-sine-wave, 10 ms (see Notes 1 and 2) Junction temperature Storage temperature range IGSM TJ Tstg ITSM 25, 85°C ITSP A SYMBOL VDRM VGKRM VALUE -100 -85 UNIT V
NOTES: 1. Initially the protector must be in thermal equilibrium with TJ 85°C, unless otherwise specified. The surge may be repeated after the device returns to its initial conditions. See the applications section for the details of the impulse generators. 2. The rated current values may be applied to either the R-G or T-G terminal pairs. Additionally, both terminal pairs may have their rated current values applied simultaneously (in this case the G terminal current will be twice the rated current value of an individual terminal pair). Above 85°C, derate linearly to zero at 150°C lead temperature.
PARAMETER ID V(BO) VGK(BO) Off-state current Breakover voltage Gate-cathode voltage at breakover On-state voltage Forward voltage Peak forward recovery voltage Holding current Gate reverse current Gate trigger current Gate trigger voltage -85 V, VGK 0 V TEST CONDITIONS = 70°C MIN TYP MAX µA mA UNIT µA V
A, 10/1000 µs, 1 kV, 33 , di/dt(i) = 8 A/µs (see Note A, 10/700 µs, 1.5 kV, RS= 10 , di/dt(i) = 14 A/µs (see Note A, 1.2/50 µs, 1.5 kV, RS= 10 , di/dt(i) = 70 A/µs (see Note A, 2/10 µs, 2.5 kV, RS= 61 , di/dt(i) = 40 A/µs (see Note A, 10/1000 µs, 1 kV, 33 , di/dt(i) = 8 A/µs (see Note A, 10/700 µs, 1.5 kV, RS= 10 , di/dt(i) = 14 A/µs (see Note A, 1.2/50 µs, 1.5 kV, RS= 10 , di/dt(i) = 70 A/µs (see Note A, 2/10 µs, 2.5 kV, RS= 61 , di/dt(i) = 40 A/µs (see Note 1 A, di/dt = -1A/ms, VGG -48 V VGG V, K and A terminals connected 3 A, tp(g) 20 µs, VGG 3 A, tp(g) 20 µs, VGG -48 V
3: All tests have 220 nF and VGG RS is the current limiting resistor between the output of the impulse generator and the or T terminal. See the applications section for the details of the impulse generators.electrical characteristics, = 25°C (unless otherwise noted) (Continued)
PARAMETER CAK Anode-cathode offstate capacitance TEST CONDITIONS = 1 MHz, = 0, (see Note -48 V MIN TYP MAX 100 50 UNIT pF
4: These capacitance measurements employ a three terminal capacitance bridge incorporating a guard circuit. The unmeasured device terminals are a.c. connected to the guard terminal of the bridge.
PARAMETER RJA Junction to free air thermal resistance TEST CONDITIONS Ptot cm2, FR4 PCB D Package P Package MIN TYP MAX 170 125 UNIT °C/W+i IFSP |ITSP|) Quadrant I Forward Conduction Characteristic
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