|Description||Dual-gate Unidirectional Overvoltage Protector|
|Datasheet||Download TISP83121D datasheet
Programmable Protection Configurations ±100 V Typically 5 Lines Protected by Two TISP83121D + Diode Steering Networks High Surge Current 8/20 µs Pin compatible with the LCP3121 - Functional Replacement in Diode Steering Network Applications - 50% more surge current Small Outline Surface Mount Package - Available Ordering OptionsFor operation at the rated current values connect pins 4, 5 and 8 together.
The is a dual-gate reverse-blocking unidirectional thyristor designed for the protection of dual-voltage ringing SLICs (Subscriber Line Interface Circuits) against overvoltages on the telephone line caused by lightning, a.c. power contact and induction. The device chip is a four-layer NPNP silicon thyristor structure which has an electrode connection to every layer. For negative overvoltage protection the TISP83121D is used in a common anode configuration with the voltage to be limited applied to the cathode (K) terminal and the negative reference potential applied to the gate 1 (G1) terminal. For positive overvoltage protection the TISP83121D is used in a common cathode configuration with the voltage to be limited applied to the anode (A) terminal and the positive reference potential applied to the gate 2 (G2) terminal. The is a unidirectional protector and to prevent reverse bias, requires the use of a series diode between the protected line conductor and the protector. Further, the gate reference supply voltage requires an appropriately poled series diode to prevent the
Under low level power cross conditions the TISP83121D gate current will charge the gate reference supply. If the reference supply cannot absorb the charging current its potential will increase, possibly to damaging levels. To avoid excessive voltage levels a clamp (zener or avalanche breakdown diode) may be added in shunt with the supply. Alternatively, a grounded collector emitter-follower may be used to reduce the charging current by the transistors HFE value. This monolithic protection device is made with a ion-implanted epitaxial-planar technology to give a consistent protection performance and be virtually transparent to the system in normal operation.
Information is current as of publication date. Products conform to specifications in accordance with the terms of Power Innovations standard warranty. Production processing does not necessarily include testing of all parameters.
RATING Repetitive peak off-state voltage, 70 °C Non-repetitive peak on-state pulse current (see Notes 1 and µs (GR-1089-CORE, open-circuit voltage wave shape 10/1000 µs) 5/310 µs (CCITT K20/21, open-circuit voltage wave shape 7 kV10/700 µs) 8/20 µs (ANSI C62.41, open-circuit voltage wave shape 1.2/50 µs) Non-repetitive peak on-state current, 50 Hz, halfwave rectified sinewave, (see Notes 1 and 900 s Junction temperature Storage temperature range TJ Tstg ITSM °C A ITSP 500 A SYMBOL V DRM VALUE 100 UNIT V
NOTES: 1. Initially the protector must be in thermal equilibrium with < 70 °C. The surge may be repeated after the device returns to its initial conditions. For operation at the rated current value, pins 4, 5 and 8 must be connected together. 2. Above 70 °C, derate linearly to zero 150 °C lead temperature.
PARAMETER ID IDRM Off-state current Repetitive peak off-state current Holding current Reverse current Vd = VDRM VG1T VG2T CAK NOTE 1 A, di/dt 70 °C Gate G1 trigger current +1 A, tp(g) 20 µs Gate G2 trigger current +1 A, tp(g) µs G1-K trigger voltage G2-A trigger voltage Anode to cathode offstate capacitance +1 A, tp(g) +1 A, tp(g) = 1 MHz, = 1 VRMS, = 0 (see Note V pF TEST CONDITIONS MIN TYP MAX 300 mA UNIT µA
3: These capacitance measurements employ a three terminal capacitance bridge incorporating a guard circuit. The unmeasured device terminals are decoupled to the guard terminal of the bridge.
PARAMETER RJA Junction to free air thermal resistance TEST CONDITIONS = 25 °C, EIA/JESD51-3 PCB, EIA/JESD51-2 environment, = ITSM(900) MIN TYP MAX 105 UNIT °C/W
Figure 2 shows two TISP83121D devices protecting many lines. Line conductor positive overvoltage protection is given by the steering diode array connected to the anode of the upper TISP83121D and the TISP83121D itself. The TISP83121D gate reference voltage is the positive battery supply, +VBAT. The initial limiting voltage will be the sum of the voltages of the battery, the forward biased conductor diode, the gate trigger of the TISP83121D and the forward biased reference voltage blocking diode. Typically the conductor voltage will be initially limited 2.5 V above the +VBAT value. Line conductor negative overvoltage protection is given by the diode steering array connected to the cathode of the lower TISP83121D and the TISP83121D itself. The TISP83121D gate reference voltage is the negative battery supply, -VBAT. The initial limiting voltage will be the sum of the voltages of the battery, the forward biased conductor diode, the gate trigger of the TISP83121D and the forward biased reference voltage blocking diode. Typically the conductor voltage will be initially limited 2.5 V below the -VBAT value. When an TISP83121D crowbars and grounds all conductors of the appropriate polarity, the device current will be the sum of all the SLIC output currents. This will usually exceed the TISP83121D holding current. To switch off the TISP83121D and restore normal operation, the grounded condition of the SLIC output must be detected and the SLIC outputs turned off. The 150 A rating of the TISP83121D allows a large number of lines to be protected against currents caused by lightning. For example, if a recommendation K.20 10/700 generator was connected to all lines, together
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