Details, datasheet, quote on part number: M68AR016DN70ZB1T
PartM68AR016DN70ZB1T
CategoryMemory => SRAM
Description16 Mbit 1m X16 1.8v Asynchronous SRAM
CompanyST Microelectronics, Inc.
DatasheetDownload M68AR016DN70ZB1T datasheet
  

 

Features, Applications

I/O SUPPLY VOLTAGE: 1.95V 1M WORDS x 16 bits LOW POWER SRAM EQUAL CYCLE and ACCESS TIME: 70ns LOW VCC DATA RETENTION: 1.0V LOW STANDBY CURRENT TRI-STATE COMMON I/O SINGLE BYTE READ/WRITE AUTOMATIC POWER DOWN

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

TABLE OF CONTENTS SUMMARY DESCRIPTION. 3 Figure 2. Logic Diagram. 3 Table 1. Signal Names. 3 Figure 3. TFBGA Connections (Top view through package). 4 Figure 4. Block Diagram. 5 MAXIMUM RATING. 5 Table 2. Absolute Maximum Ratings. 5 DC AND AC PARAMETERS. 6 Table 3. Operating and AC Measurement Conditions. 6 Figure 5. AC Measurement I/O Waveform. 6 Figure 6. AC Measurement Load Circuit. 6 Table 4. Capacitance. 7 Table 5. DC Characteristics. 7 OPERATION. 8 Table 6. Operating Modes. 8 Read Mode. 8 Figure 7. Address Controlled, Read Mode AC Waveforms. 8 Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. 9 Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms. 9 Table 7. Read and Standby Mode AC Characteristics. 10 Write Mode. 11 Figure 10. Write Enable Controlled, Write AC Waveforms. 11 Figure 11. Chip Enable E1 Controlled, Write AC Waveforms. 12 Figure 12. UB/LB Controlled, Write AC Waveforms. 12 Table 8. Write Mode AC Characteristics. 13 Figure 13. E1 Controlled, Low VCC Data Retention AC Waveforms. 14 Figure 14. E2 Controlled, Low VCC Data Retention AC Waveforms. 14 Table 9. Low VCC Data Retention Characteristics. 14 PACKAGE MECHANICAL. 15 Figure - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline. 15 Table - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. 16 PART NUMBERING. 17 Table 12. Ordering Information Scheme. 1 7 REVISION HISTORY. 18 Table 13. Document Revision History. 18

SUMMARY DESCRIPTION The a 16 Mbit (16,777,216 bit) Low Power SRAM fabricated in STMicroelectronics advanced CMOS technology, organized as 1,048,576 words by 16 bits. The device exhibits fully static operation requiring no external clocks or timing strobes. It needs to 1.95V supply voltage. By using the VCCQ pin all the outputs can be powered independently from the core supply voltage allowing to drive the I/O pins down 1.5V. V CCQ pin can be tied to Vcc if the feature is not required.

This device has a standard Asynchronous SRAM Interface. Read and Write cycles can be performed on a single byte by using UB/LB signals. The device can be put into standby mode by using E1/E2 pins. The same pins can be used to cascade more devices in order to achieve deep memory expansion. Standby mode allows a low current consumption, 99%, by reducing internal activities. The M68AR024D is available (0.75 mm pitch) package with industrial standard footprint.

A0-A19 DQ0-DQ15 Address Inputs Data Input/Output Chip Enables Output Enable Write Enable Upper Byte Enable Input Lower Byte Enable Input Supply Voltage I/O Supply Voltage Ground Not Connected Internally Don't Use as Internally Connected


 

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