Details, datasheet, quote on part number: M68AR512DN70ZB6T
PartM68AR512DN70ZB6T
CategoryMemory => SRAM
Description8 Mbit 512k X16 1.8v Asynchronous SRAM
CompanyST Microelectronics, Inc.
DatasheetDownload M68AR512DN70ZB6T datasheet
  

 

Features, Applications

x 16 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 70ns SINGLE BYTE READ/WRITE LOW STANDBY CURRENT LOW VCC DATA RETENTION: 1.0V TRI-STATE COMMON I/O AUTOMATIC POWER DOWN DUAL CHIP ENABLE for EASY DEPTH EXPANSION

TABLE OF CONTENTS SUMMARY DESCRIPTION. 3 Figure 2. Logic Diagram. 3 Table 1. Signal Names. 3 Figure 3. TFBGA Connections (Top view through package). 4 Figure 4. Block Diagram. 5 MAXIMUM RATING. 5 Table 2. Absolute Maximum Ratings. 5 DC and AC PARAMETERS. 6 Table 3. Operating and AC Measurement Conditions. 6 Figure 5. AC Measurement I/O Waveform. 6 Figure 6. AC Measurement Load Circuit. 6 Table 4. Capacitance. 7 Table 5. DC Characteristics. 7 OPERATION. 8 Table 6. Operating Modes. 8 Read Mode. 8 Figure 7. Address Controlled, Read Mode AC Waveforms. 8 Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. 9 Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms. 9 Table 7. Read and Standby Mode AC Characteristics. 10 Write Mode. 11 Figure 10. Write Enable Controlled, Write AC Waveforms. 11 Figure 11. Chip Enable Controlled, Write AC Waveforms. 12 Figure 12. UB/LB Controlled, Write AC Waveforms. 12 Table 8. Write Mode AC Characteristics. 13 Figure 13. E1 Controlled, Low VCC Data Retention AC Waveforms. 14 Figure 14. E2 Controlled, Low VCC Data Retention AC Waveforms. 14 Table 9. Low VCC Data Retention Characteristics. 14 PACKAGE MECHANICAL. - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline. - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline. - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. 16 PART NUMBERING. 17 Table 12. Ordering Information Scheme. 1 7 REVISION HISTORY. 18 Table 13. Document Revision History. 18

SUMMARY DESCRIPTION The an 8 Mbit (8,388,608 bit) CMOS SRAM, organized as 524,288 words by 16 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 1.8V (150mV) supply. This device has a Chip Select pin (E2) for easy memory expansion; when it is active (E2 high) the device has an auto-

matic power-down feature, reducing the power consumption by over 99%. The M68AR512D is available TFBGA48 (6x7mm and 8x10mm, 6x8 active ball array, 0.75 mm ball pitch) package. See the Ordering Information Scheme (Table 12) for details.

A0-A18 Address Inputs Data Input/Output Chip Enable Output Enable Write Enable Upper Byte Enable Input Lower Byte Enable Input Supply Voltage Ground Not Connected Don't Use as Internally Connected


 

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