Details, datasheet, quote on part number: SN74ALS233BFN
PartSN74ALS233BFN
CategorySemiconductors => Logic => Flip-Flop/Latch/Register => FIFO Register
Part familySN74ALS233B 16 x 5 asynchronous FIFO memory
TitleAsynchronous FIFOs
Description16 x 5 asynchronous FIFO memory 20-PLCC 0 to 70
CompanyTexas Instruments, Inc.
StatusOBSOLETE
ROHSNot Compliant
SampleNo
DatasheetDownload SN74ALS233BFN datasheet
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  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
20FNPLCCS-PQCC-J 8.968.964.061.27
Application notes
• Advanced Schottky (ALS and AS) Logic Families
This document introduces the advanced Schottky family of clamped TTL integrated circuits (ICs). Detailed electrical characteristics of the 'AS and 'ALS devices with table formats are provided. Guidelines for designing high-performance digital systems using | Doc

 

Features, Applications

Independent Asychronous Inputs and Outputs 16 Words by 5 Bits Data Rates From to 40 MHz Fall-Through Time 14 ns Typ 3-State Outputs Package Options Include Plastic Small-Outline Package (DW), Plastic Chip Carriers (FN), and Standard Plastic 300-mil DIPs (N)

description

This 80-bit memory uses advanced low-power Schottky technology and features high speed and a fast fall-through time. It is organized as 16 words by 5 bits. A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. This FIFO is designed to process data at rates to 40 MHz in a bit-parallel format, word by word. Data is written into memory on a low-to-high transition at the load clock (LDCK) input and is read out on a low-to-high transition at the unload clock (UNCK) input. The memory is full when the number of words clocked in exceeds by 16 the number of words clocked out. When the memory is full, LDCK signals have no effect. When the memory is empty, UNCK signals have no effect.

Status of the FIFO memory is monitored by the FULL, EMPTY, FULL­1, and EMPTY+1 output flags. The FULL output is low when the memory is full and high when it is not full. The FULL­1 output is low when the memory contains 15 data words. The EMPTY output is low when the memory is empty and high when it is not empty. The EMPTY+1 output is low when one word remains in memory. A low level on the reset (RST) input resets the internal stack control pointers and also sets EMPTY low and sets FULL, FULL­1, and EMPTY+1 high. The Q outputs are not reset to any specific logic level. The first low-to-high transition on LDCK, after either a RST pulse or from an empty condition, causes EMPTY to go high and the data to appear on the Q outputs. It is important to note that the first word does not have to be unloaded. Data outputs are noninverting with respect to the data inputs and are at high impedance when the output-enable (OE) input is low. OE does not affect the output flags. Cascading is easily accomplished in the word-width direction but is not possible in the word-depth direction. The SN74ALS233B is characterized for operation from to 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. The symbol is functionally accurate but does not show the details of implementation; for these, see the logic diagram. The symbol represents the memory if it were controlled by a single counter whose content is the number of words stored at the time. Output data is invalid when the counter content (CT) is 0.


 

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