|Category||Semiconductors => Logic => Flip-Flop/Latch/Register => FIFO Register|
|Part family||SN74ALS235 64 x 5 Asynchronous FIFO memory|
|Description||64 x 5 Asynchronous FIFO memory 20-PDIP 0 to 70|
|Company||Texas Instruments, Inc.|
|Datasheet||Download SN74ALS235N datasheet
|Cross ref.||Similar parts: 72413L25P, 72413L35P|
|Pin nb||Package type||Ind std||JEDEC code||Package qty||Carrier||Device mark||Width (mm)||Length (mm)||Thick (mm)||Pitch (mm)|
|• Advanced Schottky (ALS and AS) Logic Families
This document introduces the advanced Schottky family of clamped TTL integrated circuits (ICs). Detailed electrical characteristics of the 'AS and 'ALS devices with table formats are provided. Guidelines for designing high-performance digital systems using | Doc
Asynchronous Operation Organized as 64 Words by 5 Bits Data Rates From to 25 MHz 3-State Outputs Package Options Include Plastic Small-Outline Packages (DW), Plastic J-Leaded Chip Carriers (FN), and Standard Plastic 300-mil DIPs (N)description
The a 320-bit memory utilizing advanced low-power Schottky IMPACTTM technology. It features high speed with fast fall-through times and is organized as 64 words by 5 bits. A first-in, first-out (FIFO) memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ALS235 is designed to process data at rates from to 25 MHz in a bit-parallel format, word by word.
15 7 Data is written into memory on the rising edge 14 8 the shift-in (SI) input. When SI goes low, the first data word ripples through to the output (see Figure 1). As the FIFO fills up, the data words stack up in the order they were written. When the FIFO is full, additional shift-in pulses have no effect. Data is shifted out of memory on the falling edge of the shift-out (SO) input (see Figure 2). When the FIFO is empty, additional SO pulses have no effect. The last data word remains at the outputs until a new word falls through or reset (RST) goes low.
Status of the SN74ALS235 FIFO memory is monitored by the output-ready (OR), input-ready (IR), almost-full/ almost-empty (AF/AE), and half-full (HF) flags. When OR is high, valid data is available at the outputs. OR is low when SO is high and stays low when the FIFO is empty. IR is high when the inputs are ready to receive more data. IR is low when SI is high and stays low when the FIFO is full. AF/AE is high when the FIFO contains eight or less words (see Figure 56 or more words (see Figure 6). AF/AE is low when the FIFO contains between nine and 55 words. HF is high when the FIFO contains 32 or more words and is low when the FIFO contains 31 words or less (see Figure 7). When the FIFO is empty, input data is shifted to the output automatically when SI goes low. SO is held high during this time, the OR flag pulses high indicating valid data at the outputs (see Figure 3). When the FIFO is full, data can be shifted in automatically by holding SI high and taking SO low. One propagation delay after SO goes low, IR will go high. SI is still high when IR goes high, data at the inputs are automatically shifted in. Since IR is normally low when the FIFO is full and SI is high, only a high-level pulse is seen on the IR output.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. IMPACT is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
The FIFO must be reset after power up with a low-level pulse on the master reset (RST) input. This sets IR high and OR low signifying that the FIFO is empty. Resetting the FIFO sets the outputs to a low logic level (see Figure SI is high when RST goes high, the input data is shifted in and IR goes low and remains low until SI goes low. If SI goes low before RST goes high, the input data will not be shifted in and IR goes high. Data outputs are noninverting with respect to the data inputs and are at high impedance when the output-enable (OE) input is high. OE does not affect the status-flag outputs (see Figure 2). The SN74ALS235 is characterized for operation from to 70°C.This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12.
|Some Part number from the same manufacture Texas Instruments, Inc.|
|SN74ALS236DW 64 4 Asynchronous First-in, First-out Memory|
|SN74ALS236N ti SN74ALS236, 64 X 4 Asynchronous Fifo Memory|
|SN74ALS240A Octal Buffer/driver With 3-state Outputs|
|SN74ALS240A-1DBR ti SN74ALS240A-1, Octal Buffer/bus Drivers|
|SN74ALS240ADW ti SN74ALS240A, Octal Buffers/drivers With 3-State Outputs|
|SN74ALS241A-1DW ti SN74ALS241A, Octal Buffers/drivers With 3-State Outputs|
|SN74ALS241BDW ti SN74ALS241B, Octal Buffers/drivers With 3-State Outputs|
|SN74ALS241C Octal Buffers/drivers With 3-state Outputs|
|SN74ALS241C-1DW ti SN74ALS241C, Octal Buffers/drivers With 3-State Outputs|
|SN74ALS243A Quad Bus Transceivers With 3-state Outputs|
|SN74ALS243A-1N ti SN74ALS243A, Quadruple Bus Transceivers With 3-State Outputs|
|SN74ALS244A-1N ti SN74ALS244A, Octal Buffers/line Drivers With 3-State Outputs|
|SN74ALS244BDBLE ti SN74ALS244B, Octal Buffers/line Drivers With 3-State Outputs|