Details, datasheet, quote on part number: SN74ALS236N
PartSN74ALS236N
CategorySemiconductors => Logic => Flip-Flop/Latch/Register => FIFO Register
Part familySN74ALS236 64 x 4 asynchronous FIFO memory
TitleAsynchronous FIFOs
Description64 x 4 asynchronous FIFO memory 16-PDIP 0 to 70
CompanyTexas Instruments, Inc.
StatusACTIVE
ROHSCompliant
SampleNo
DatasheetDownload SN74ALS236N datasheet
Cross ref.Similar parts: 72401L10P, 72401L15P, 72401L25P, 72401L45P, 72403L10P, 72403L15P, 72403L25P, 72403L35P, 72403L45P, IDT72401L25P
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Specifications 
Schmitt TriggerNo
Package GroupPDIP
Approx. Price (US$)7.35 | 1ku
  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
16NPDIPR-PDIP-T25TUBESN74ALS236N 6.3519.33.92.54
Application notes
• Advanced Schottky (ALS and AS) Logic Families
This document introduces the advanced Schottky family of clamped TTL integrated circuits (ICs). Detailed electrical characteristics of the 'AS and 'ALS devices with table formats are provided. Guidelines for designing high-performance digital systems using | Doc
• Power-Dissipation Calculations for TI FIFO Products (Rev. A)
Low power consumption is a major advantage of TI FIFO products. Power calculations are required to meet design requirements for chip temperature and system power. This document assists component and system designers in evaluating power consumption for the | Doc

 

Features, Applications

Asynchronous Operation Organized as 64 Words by 4 Bits Data Rates to 30 MHz 3-State Outputs Package Options Include Plastic Small-Outline Package (DW), Plastic J-Leaded Chip Carriers (FN), and Standard Plastic 300-mil DIPs (N)

description

The a 256-bit memory utilizing advanced low-power Schottky IMPACTTM technology. It features high speed with fast fall-through times and is organized as 64 words by 4 bits. A first-in, first-out (FIFO) memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ALS236 is designed to process data at rates to 30 MHz in a bit-parallel format, word by word.

Data is written into memory on the rising edge of the shift-in (SI) input. When SI goes low, the first data word ripples through to the output (see Figure 1). As the FIFO fills up, the data words ­ No internal connection stack up in the order they were written. When the FIFO is full, additional shift-in pulses have no effect. Data is shifted out of memory on the falling edge of the shift-out (SO) input (see Figure 2). When the FIFO is empty, additional SO pulses have no effect. The last data word remains at the outputs until a new word falls through or reset (RST) goes low. Status of the SN74ALS236 FIFO memory is monitored by the output-ready (OR) and input-ready (IR) flags. When OR is high, valid data is available at the outputs. OR is low when SO is high and stays low when the FIFO is empty. IR is high when the inputs are ready to receive more data. IR is low when SI is high and stays low when the FIFO is full. When the FIFO is empty, input data is shifted to the output automatically when SI goes low. SO is held high during this time, the OR flag pulses high, indicating valid data at the outputs (see Figure 3). When the FIFO is full, data is shifted in automatically by holding SI high and taking SO low. One propagation delay after SO goes low, IR goes high. SI is still high when IR goes high, data at the inputs is automatically shifted in. Since IR is normally low when the FIFO is full and SI is high, only a high-level pulse is seen on the IR output (see Figure 4).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. IMPACT is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

The FIFO must be reset after power up with a low-level pulse on the master reset (RST) input. This sets IR high and OR low, signifying that the FIFO is empty. Resetting the FIFO sets the outputs to a low logic level (see Figure SI is high when RST goes high, the input data is shifted in and IR goes low and remains low until SI goes low. If SI goes low before RST goes high, the input data is not shifted in and IR goes high. Data outputs are noninverting with respect to the data inputs. The SN74ALS236 is characterized for operation from to 70°C.

This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW and N packages.



 

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