|Category||Semiconductors => Logic => Buffer/Driver/Transceiver => Inverting Buffer/Driver|
|Part family||SN74ALS29825 8-Bit Bus Interface Flip-Flops With 3-State Outputs|
|Title||Inverting Buffers and Drivers|
|Description||8-Bit Bus Interface Flip-Flops With 3-State Outputs 24-SOIC 0 to 70|
|Company||Texas Instruments, Inc.|
|Datasheet||Download SN74ALS29825DW datasheet
|Pin nb||Package type||Ind std||JEDEC code||Package qty||Carrier||Device mark||Width (mm)||Length (mm)||Thick (mm)||Pitch (mm)|
|• Advanced Schottky (ALS and AS) Logic Families
This document introduces the advanced Schottky family of clamped TTL integrated circuits (ICs). Detailed electrical characteristics of the 'AS and 'ALS devices with table formats are provided. Guidelines for designing high-performance digital systems using | Doc
Functionally Equivalent to AMD AM29825 and AM29826 Improved IOH Specifications Multiple Output Enables Allow Multiuser Control of the Interface Outputs Have Undershoot Protection Circuitry Power-Up High-Impedance State Package Options Include Plastic "Small-Outline" Packages and Standard Plastic and Ceramic 300-mil DIPs Buffered Control Inputs to Reduce DC Loading Effectdescription
These 8-bit flip-flops feature three-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing multiuser registers, I/O ports, bidirectional bus drivers, and working registers. With the clock enable (CLKEN) low, the eight D-type edge-triggered flip-flops enter data on the low-to- high transitions of the clock. Taking CLKEN high will disable the clock buffer, thus latching the outputs. The ALS29825 has noninverting D inputs and the ALS29826 has inverting D inputs. Taking the CLR input low causes the eight Q outputs to go low independently of the clock.
Multiuser buffered output-control inputs (OC1, OC2, and OC3) can be used to place the eight outputs in either a normal logic state (high or low level) or a high-impedance state. The outputs are also in the high-impedance state during power-up and power-down conditions. The outputs remain in the high-impedance state while the device is powered-down. In the high-impedance state the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive the bus lines in a bus-organized system without need for interface or pullup components. The output controls do not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54ALS29825 is characterized over the full military range to 125°C. The SN74ALS29825 and SN74ALS29826 are characterized for operation from to 70°C.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303This symbol is in accordance with ANSI/IEEE Std. 91-1984 and IEC Publication 617-12.
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