|Category||Semiconductors => Logic => Buffer/Driver/Transceiver => Parity Transceiver|
|Part family||SN74ALS29854 8-Bit To 9-Bit Parity Bus Transceivers|
|Description||8-Bit To 9-Bit Parity Bus Transceivers 24-PDIP 0 to 70|
|Company||Texas Instruments, Inc.|
|Datasheet||Download SN74ALS29854NT3 datasheet
|Pin nb||Package type||Ind std||JEDEC code||Package qty||Carrier||Device mark||Width (mm)||Length (mm)||Thick (mm)||Pitch (mm)|
|• Advanced Schottky (ALS and AS) Logic Families
This document introduces the advanced Schottky family of clamped TTL integrated circuits (ICs). Detailed electrical characteristics of the 'AS and 'ALS devices with table formats are provided. Guidelines for designing high-performance digital systems using | Doc
Functionally Similar to AMD's AM29854 High-Speed Bus Transceiver With Parity Generator/Checker Parity-Error Flag With Open-Collector Outputs Latch for Storing the Parity-Error Flag Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (NT) 300-mil DIPsdescription
The to 9-bit parity 11 14 transceiver designed for two-way communication 12 13 between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the parity-error (ERR) output indicates whether or not an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device so that the buses are effectively isolated. A 9-bit parity generator / checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with an open-collector ERR flag. ERR can be either passed, sampled, stored, or cleared from the latch using the latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability. The SN74ALS29854 is characterized for operation from to 70°C.
FUNCTION TABLE INPUTS OEB OEA CLR of Hs Odd Even NA Odd H Even Odd Even Ls NA Odd Even B X OUTPUT AND I/O A NA PARITY L NA ERR H NA OPERATION
A data to B bus and generate parity B data to A bus and check parity Store error flag Clear error-flag register Isolation§
NA = not applicable, = no change, X = don't care Summation of high-level inputs includes PARITY along with Bi inputs. Output states shown assume ERR was previously high. § In this mode, ERR, when enabled, shows inverted parity of the A bus.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
ERROR-FLAG FUNCTIONS INPUTS LE L CLR L INTERNAL TO DEVICE POINT OUTPUT PRESTATE ERRn1 OUTPUT ERR Pass FUNCTIONERRn1 represents the state of ERR before any changes at CLR, LE, or point P.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC. 7 V Input voltage, VI. 7 V Voltage applied to a disabled I/O port. 5.5 V Operating free-air temperature range, TA. to 70°C Storage temperature range. to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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