Details, datasheet, quote on part number: TLC2578IDW
CategorySemiconductors => Data Converters => Analog-to-Digital Converters (ADCs) => Precision ADCs (<=10MSPS)
Part familyTLC2578 Serial Out, Low Power with Built-In Conversion Clock & 8x FIFO, 8 Channels
DescriptionSerial Out, Low Power with Built-In Conversion Clock & 8x FIFO, 8 Channels 24-SOIC -40 to 85
CompanyTexas Instruments, Inc.
DatasheetDownload TLC2578IDW datasheet
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Digital Supply(Min)(V)2.7
Package GroupSOIC,TSSOP
Power Consumption(Typ)(mW)29
Operating Temperature Range(C)-40 to 85
Input Range(Min)(V)-10
Multi-Channel ConfigurationMultiplexed
Analog Voltage AVDD(Max)(V)5.5
Sample Rate (max)(SPS)200kSPS
Digital Supply(Max)(V)5.5
Sample Rate(Max)(MSPS)0.2
# Input Channels8
Reference ModeExt
Input TypePseudo-Differential,Single-Ended
Approx. Price (US$)7.61 | 1ku
Analog Voltage AVDD(Min)(V)4.75
Input Range(Max)(V)10
  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
24DWSOICR-PDSO-G25TUBETLC2578I 7.515.42.351.27
Application notes
• Determining Minimum Acquisition Times for SAR ADCs, part 2
The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied | Doc


Features, Applications


14-Bit Resolution for TLC3574/78, 12-Bit for TLC2574/2578 Maximum Throughput 200-KSPS Multiple Analog Inputs: ­ 8 Single-Ended Channels for ­ 4 Single-Ended Channels for TLC3574/2574 Analog Input Range: ±10 V Pseudodifferential Analog Inputs SPI/DSP-Compatible Serial Interfaces With SCLK to 25-MHz Built-In Conversion Clock and 8x FIFO Single 5-V Analog Supply; 3-/5-V Digital Supply Low-Power mA in Normal Operation µA in Power Down Programmable Autochannel Sweep and Repeat Hardware-Controlled, Programmable Sampling Period Hardware Default Configuration INL: TLC3574/78: ±1 LSB; TLC2574/78: ±0.5 LSB DNL: TLC3574/78: ±0.5 LSB; TLC2574/78: ±0.5 LSB SINAD: TLC3574/78: 79 dB; 72 dB THD: TLC3574/78: ­82 dB; ­82 dB


The TLC3578, TLC2574, and TLC2578 are a family of high-performance, low-power, CMOS analog-to-digital converters (ADC). a 14-bit ADC; a 12-bit ADC. All parts operate from single 5-V analog power supply and to 5-V digital supply. The serial interface consists of four digital input [chip select (CS), frame sync (FS), serial input-output clock (SCLK), serial data input (SDI)], and a 3-state serial data output (SDO). CS (works as SS, slave select), SDI, SDO and SCLK form an SPI interface. FS, SDI, SDO, and SCLK form DSP interface. The frame sync signal (FS) indicates the start of a serial data frame being transferred. When multiple converters connect to one serial port of a DSP, CS works as the chip select to allow the host DSP to access the individual converter. CS can be tied to ground if only one converter is used. FS must be tied to DVDD it is not used (such in an SPI interface). When SDI is tied to DVDD, the device is set in hardware default mode after power on and no software configuration is required. In the simplest case, only three wires (SDO, SCLK, and CS or FS) are needed to interface with the host.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.


In addition to being a high-speed ADC with versatile control capability, these devices have an on-chip analog multiplexer (MUX) that can select any analog input or one of three self-test voltages. The sample-and-hold function is automatically started after the fourth SCLK (normal sampling) or can be controlled by a special pin, CSTART, to extend the sampling period (extended sampling). The normal sampling period can also be programmed as short sampling (12 SCLKs) or long sampling (44 SCLKs) to accommodate the faster SCLK operation popular among high-performance signal processors. The TLC3574/78 and TLC2574/78 are designed to operate with low-power consumption. The power saving feature is further enhanced with autopower-down mode and programmable conversion speeds. The conversion clock (internal OSC) is built in. The converter can also use an external SCLK as the conversion clock for maximum flexibility. The TLC3574/78 and TLC2574/78 are specified with bipolar input and a full scale range ±10 V.


DGND AGND TLC3574, TLC2574 NOTE: 4-Bit counter counts the CLOCK, SCLK. The CLOCK is gated by CS falling edge if CS initiates the conversion operation cycle, or gated in by the rising edge if FS initiates the operation cycle. SCLK is disabled for serial interface when CS is high.


REFP Bipolar Signal Scaling MUX 9.9 k Ain 1.5 k Ron C(sample)= 30 pF Equivalent Digital Input Circuit Digital Input VDD

REFM Diode Turn on Voltage: 35 V Equivalent Analog Input Circuit

TERMINAL NO. NAME TLC2578 I Analog signal inputs. Analog input signals applied to these terminals are internally multiplexed. The driving source impedance should be less than or equal to 25 for normal sampling. For larger source impedance, use the external hardware conversion start signal CSTART (the low time of CSTART controls the sampling period) or reduce the frequency of SCLK to increase the sampling time. I/O DESCRIPTION

Analog ground return for the internal circuitry. Unless otherwise noted, all analog voltage measurements are with respect to AGND. Analog supply voltage Internal compensation pin. Install compensation capacitors 0.1 µF between this pin and AGND. Chip select. When CS is high, SDO is in high-impedance state, SDI is ignored, and SCLK is disabled to clock data, but works as conversion clock source if programmed. The falling edge of CS input resets the internal 4-bit counter, enables SDI and SCLK, and removes SDO from high-impedance state. FS is high at CS falling edge, CS falling edge initiates the operation cycle. CS works as slave select (SS) to provide an SPI interface. FS is low at CS falling edge, FS rising edge initiates the operation cycle. CS can be used as chip select to allow host to access the individual converter.

External sampling trigger signal, which initiates the sampling from a selected analog input channel when the device works in extended sampling mode (asynchronous sampling). A high-to-low transition starts the sampling of the analog input signal. A low-to-high transition puts the S/H in hold mode and starts the conversion. The low time of the CSTART signal controls the sampling period. CSTART signal must stay low long enough for proper sampling. CSTART must stay high long enough after the low-to-high transition for the conversion to finish maturely. The activation of CSTART is independent of SCLK and the level of CS and FS. However, the first CSTART cannot be issued before the rising edge of the eleventh SCLK. Tie this pin to DVDD if not used. Digital ground return for the internal circuitry Digital supply voltage


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