Details, datasheet, quote on part number: TMS28F400BZB90BDBJL
CategorySemiconductors => Memory => Flash
Part familyTMS28F400BZB 262 144 By 16-Bit, 524 288 By 8-Bit Boot-Block Flash Memory
Descriptionti TMS28F400BZB, 262 144 BY 16-Bit, 524 288 BY 8-Bit Boot-block Flash Memory
CompanyTexas Instruments, Inc.
ROHSNot Compliant
DatasheetDownload TMS28F400BZB90BDBJL datasheet
  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
44DBJ 13.328.22.13


Features, Applications

by 8 Bits by 16 Bits Array-Blocking Architecture Two 8K-Byte Parameter Blocks One 96K-Byte Main Block Three 128K-Byte Main Blocks One 16K-Byte Protected Boot Block Top or Bottom Boot Locations All Inputs / Outputs TTL Compatible Maximum Access/Minimum Cycle Time VCC (x = top (T) or bottom (B) boot-block configuration ordered) 10 000 Program/Erase-Cycles Two Temperature Ranges Commercial. 70C Extended. to 85C Low Power Dissipation ( VCC ) Active Write. mW ( Byte Write) Active Read. mW ( Byte Read) Active Write. mW ( Word Write) Active Read. mW ( Word Read) Block Erase. mW Standby. 0.55 mW (CMOS-Input Levels) Deep Power-Down Mode. 0.0066 mW Fully Automated On-Chip Erase and Word / Byte-Program Operations Write Protection for Boot Block Industry Standard Command State Machine (CSM) Erase Suspend/Resume Algorithm-Selection Identifier

PIN NOMENCLATURE A17 BYTE NC RP VCC VPP VSS W Address Inputs Byte Enable Data In / Out Data In / Out (word-wide mode), Low-Order Address (byte-wide mode) Chip Enable Output Enable No Internal Connection Reset / Deep Power Down 5-V Power Supply 12-V Power Supply for Program / Erase Ground Write Enable


The 194 304-bit), boot-block flash memory that can be electrically block-erased and reprogrammed. The TMS28F400BZx is organized in a blocked architecture consisting of one 16K-byte protected boot block, two 8K-byte parameter blocks, one 96K-byte main block, and three 128K-byte main blocks. The device can be ordered with either a top or bottom boot-block configuration. Operation 256K-word (16-bit) organization is user-definable.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Embedded program and block-erase functions are fully automated by an on-chip write state machine (WSM), simplifying these operations and relieving the system microcontroller of these secondary tasks. WSM status can be monitored by the on-chip status register to determine progress of program / erase tasks. The device features user-selectable block erasure. The TMS28F400BZx flash memory is offered a 44-pin PSOP. It is available in two temperature ranges: to 70C and to 85C.

80 B DBJ L Temperature Range Designator to 85C Package Designator DBJ = Plastic Small-Outline Package

Boot Block Location Indicator T = Top Location B = Bottom Location
Data Register Identification Register Output Multiplexer Status Register
Y Gating / Sensing 8K-Byte Parameter Block 96K-Byte Main Block 128K-Byte Main Block

The TMS28F400BZx uses a blocked architecture to allow independent erasure of selected memory blocks. The block to be erased is selected by using any valid address within that block. block memory maps The TMS28F400BZx is available with the block architecture mapped in either of two configurations: the boot block located at the top or at the bottom of the memory array, as required by different microprocessors. The TMS28F400BZB (bottom boot block ) is mapped with the 16K-byte boot block located at the low-order address range to 01FFFh). The TMS28F400BZT (top boot block ) is inverted with respect to the TMS28F400BZB (bottom boot block) since the boot block is located at the high-order address range to 3FFFFh). Both of these address ranges are for word-wide mode. Figure 1 and Figure 2 show the memory maps for these configurations.


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