|Category||Memory => Flash => Parallel Flash => 2M|
|Description||262 144 BY 8-bit Flash Memory|
|Company||Texas Instruments, Inc.|
|Datasheet||Download TMS29F002 datasheet
PIN NOMENCLATURE OE NC VCC VSS WE Address Inputs Data In / Data out Chip Enable Output Enable No Internal Connection Power Supply Ground Write Enabledescription
The 152-bit), 5-V single-supply, programmable read-only memory device that can be electrically erased and reprogrammed. This device is organized x 8 bits, divided into seven sectors: One 16K-byte protected-boot sector Two 8K-byte sectors One 32K-byte sector Three 64K-byte sectors
Any combination of sectors can be marked as read-only or erased. Full chip erasure is also supported. Sector data protection is afforded by methods that can disable any combination of sectors from write or read operations using standard programming equipment. An on-chip state machine provides an on-board algorithm that automatically pre-programs and erases any sector before it automatically programs and verifies program data at any specified address. The command set is compatible with that of the Joint Electronic Device Engineering Council (JEDEC) standards is compatible the warranty, JEDEC 2M-byte erasable Please be aware that an important notice and concerning availability,with standard and use inelectrically critical applications of Texas Instruments semiconductor and disclaimers thereto at the end of thisfeature data sheet. programmable read-only memoryproducts (EEPROM) command set.appears A suspend/resume allows access to
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Single Power Supply Supports 5-V 10% Read/Write Operation Organization:. By 8 Bits Array-Blocking Architecture One 16K-Byte Protected-Boot Sector Two 8K-Byte Parameter-Sectors One 32K-Byte Sector Three 64K-Byte Sectors Any Combination of Sectors Can Be Erased. Supports Full-Chip Erase Any Combination of Sectors Can Be Marked as Read-Only Boot-Code Sector Architecture T = Top Sector B = Bottom Sector Protection Hardware Protection Method That Disables Any Combination of Sectors From Write or Erase Operations Using Standard Programming Equipment Embedded Program/Erase Algorithms Automatically Pre-Programs and Erases Any Sector Automatically Programs and Verifies the Program Data at Specified Address JEDEC Standards Compatible With JEDEC Byte Pinouts Compatible With JEDEC EEPROM Command Set Fully Automated On-Chip Erase and Program Operations
100 000 Program/Erase Cycles Low Power Dissipation Low Current Consumption 40-mA Typical Active Read 60-mA Typical Program/Erase Current Less Than 100-µA Standby Current All Inputs/Outputs TTL-Compatible Erase Suspend/Resume Supports Reading Data From, or Programming Data to, a Sector Not Being Erased 40-Pin Thin Small Outline Package (TSOP) (DCD Suffix) Detection Of Program/Erase Operation Data Polling and Toggle Bit Feature of Program/Erase Cycle Completion High-Speed Data Access at 5-V VCC 70 Commercial. 80 Extended. to 85°C
unaltered memory blocks during a section-erase operation. All outputs of this device are TTL-compatible. Additionally, an erase/suspend/resume feature supports reading data from, or programming data to, a sector that is not being erased. Device operations are selected by writing JEDEC-standard commands into the command register using standard microprocessor write timings. The command register acts as an input to an internal-state machine which interprets the commands, controls the erase and programming operations, outputs the status of the device, outputs data stored in the device, and outputs the device algorithm-selection code. On initial power up, the device defaults to the read mode. The device has low power dissipation with a 40-mA active read for the byte mode, 60-mA typical program/erase current mode, and less than 100-mA standby current. These devices are offered with 70 and 80 ns access times. Table 1 and Table 2 show the sector-address ranges. The TMS29F002T/B is offered a 40-pin (DCD suffix) thin small-outline package.
Temperature Range L = Commercial E = Extended to 85°C) Package Type DCD = Thin Small-Outline Package Program/Erase Endurance 100 000 cyc 10 000 cyc Speed Option 80 ns Boot Code Selection Architecture T = Top Sector B = Bottom Sector Device Number / Description xxx 002 2M bit
This symbol is in accordance with ANSI / IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the FM package.
|Some Part number from the same manufacture Texas Instruments, Inc.|
|TMS29F002R 262 144 BY 8-bit Flash Memory|
|TMS29F002RB-10BFML ti TMS29F002RB, 262 144 BY 8-Bit Boot Block Flash Memory|
|TMS29F002RT-10BFML ti TMS29F002RT, 262 144 BY 8-Bit Boot Block Flash Memory|
|TMS29F010 131 072 BY 8-bit Flash Memory|
|TMS29F010-12C5FME ti TMS29F010, 1 048 576-Bit Flash Memory|
|TMS29F010-15 131 072 BY 8-bit Flash Memory|
|TMS29F010-70C5FME ti TMS29F010, 1 048 576-Bit Flash Memory|
|TMS29F040 524 288 BY 8-bit Flash Memory|
|TMS29F040-10C5DDE ti TMS29F040, 4 194 304-Bit Flash Memory|
|TMS29F400 524 288 BY 8-bit/262 144 BY 16-bit Flash Memory|
|TMS29LF008B ti TMS29LF008B, 8 388 608-Bit Boot-sector Flash Memories|
|TMS29LF008T ti TMS29LF008T, 8 388 608-Bit Boot-sector Flash Memory|
|TMS29LF040 ti TMS29LF040, 4 194 304-Bit Flash Memory|
|TMS29LF800B ti TMS29LF800B, 8 388 608-Bit Boot-sector Flash Memo|
|TMS29LF800T ti TMS29LF800T, 8 388 608-Bit Flash Memories|
|TMS29VF040 ti TMS29VF040, 4 194 304-BIT Flash Memory|
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A67L83181 : 256k X 16/18, 128k X 32/36 Lvttl, Flow-through Dba SRAM. Document Title X 32/36 LVTTL, Flow-through DBATM SRAM Revision History Initial issue Change fast access time from 10/11/12 ns Change set-up time from 2.5 ns Fix pin assignment error for pin 14 and pin 16 n Fast access time: 90, 83 MHz) n Direct Bus Alternation between READ and WRITE cycles allows 100% bus utilization n Signal ± 5% power supply n Individual.
CY7C1481V33-133AC : Standart Synchronous SRAM. Supports 133-MHz bus operations x 72 common I/O Fast clock-to-output times 5.5 ns (for 150-MHz device) 6.5 ns (for 133-MHz device) 7.5 ns (for 117-MHz device) 8.5 ns (for 100-MHz device) Single 3.3V 5% and +5% power supply VDD Separate VDDQ for or 2.5V Byte Write Enable and Global Write control Burst Capability--linear or interleaved burst order Automatic.
HY5DU561622T : 256M(16Mx16) DDR Sdram. This document is a general product and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 02 1 1) Separated `Function ' and `Timing diagram' parts - These are available in Web site (www.hynix.com) 3. Revision 0.6 (May. 02) 1) Input leakage.
HY62UF16804A : Super Low Power Slow SRAM. 512Kx16bit Full CMOS SRAM. 512K x16 bit 3.0V Super Low Power Full CMOS slow SRAM Revision No 04 History Initial Revision History Insert Revised - Reliability Spec Deleted Change AC Characteristics - tBLZ 5/5/5 10/10/10 Part Number is changed HY62UF16803A HY62UF16804A Marking Instruction is inserted Test Condition Changed - ILO / ISB ISB1 / VDR / ICCDR Marking Istruction Inserted.
HYM72V64636BLT8-H : ->Unbuffered DIMM. based on 32Mx8 SDRAM with LVTTL, 4 banks & 8K Refresh The HYM72V64636B(L)T8 Series are 64Mx64bits Synchronous DRAM Modules. The modules are composed of sixteen 32Mx8bits CMOS Synchronous DRAMs 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package a 168pin glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors.
HYM76V8735HGLT8-H : ->Unbuffered DIMM. based on 8Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh The Hynix HYM76V8735HGT8 Series are 8Mx72bits ECC Synchronous DRAM Modules. The modules are composed of nine 8Mx8bits CMOS Synchronous DRAMs 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package a 168pin glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors.
KMM332F803BS : Buffered DIMM. = KMM332F803BS 8Mx32 DRAM Sodimm Using 8MX8,4K Refresh,3.3V,Low Power/self-refresh ;; Density(MB) = - ;; Organization = 8Mx32 ;; Mode = Edo ;; Refresh = 2K/32ms ;; Speed(ns) = 50,60 ;; #of Pin = 72 ;; Component Composition = (8Mx8)x4 ;; Production Status = Eol ;; Comments = -.
LP62E16512-I : 512k X 16 Bit Low Voltage CMOS SRAM. Document Title X 16 BIT LOW VOLTAGE CMOS SRAM Revision History n Operating voltage: 2.2V n Access times: 70 ns (max.) n Current: Very low power version: Operating: 40mA (max.) Standby: 10µA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Data.
M463S0924BT0 : SODIMM. = M463S0924BT0 8M X 64 Sdram Udimm Based on 8M X 16, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs With SPD ;; Density(MB) = 64 ;; Organization = 8Mx64 ;; Bank/ Interface = 4B/LVTTL ;; Refresh = 4K/64ms ;; Speed = 1H,1L ;; #of Pin = 144 ;; Power = C,l ;; Component Composition = (8Mx16)x4+EEPROM ;; Production Status = Eol ;; Comments = PC100.
MBM29F040C : CMOS Flash 4m : 512kx8. Single 5.0 V read, program and erase Minimizes system level power requirements Compatible with JEDEC-standard commands Uses same software commands as E2PROMs Compatible with JEDEC-standard byte-wide pinouts 32-pin PLCC (Package suffix: PD) 32-pin TSOP(I) (Package suffix: PF) 32-pin TSOP(I) (Package suffix: PFTN Normal Bend Type, PFTR Reversed Bend.
MSU001 : Application Specific. MSu001/u001T 20" Voice Smart:, Type: MCU. The is a monolithic talking microcomputer that can memorize voice to 22 seconds using MOSEL qualified coding method(MPCM). It's an integration of traditional 4-bit microcomputer and voice chip with minimal external components. LCD driver and miscellaneous interface are provided for versatile applications. With more than 10K ROM/RAM inside, this chip.
UT65L1616-60 : Pseudo Low Power SRAM. Org. = 1Mx16 ;; Temp. ( J) = -40~85 ;; Voltage = 2.5~3.3V ;; Speed (ns) = 60/70 ;; Icc(Max) (mA) = 22 ;; Isb1(Max) (uA) = 50 ;; Package = 48TFBGA.
V436532Z04V : 256MB 144-PIN Unbuffered Sdram Sodimm, 32M X 64 3.3VOLT, 144 Pin Sodimm.
WSF512K16 : SRAM/Flash MCP. Organization = 512Kx16 ;; Speed (ns) = 35-90,70-120 ;; Volt = 5 ;; Package = 68 CQFP ;; Temp = C,i,m,q ;;.
CS18HS02563AC-12 : IC,SRAM,32KX8,CMOS,SOP,28PIN,PLASTIC. s: Memory Category: SRAM Chip. History Add green code in part no. Add in 28L TSOP 1 8x13.4mm Revise speed option and DC/AC characteristics Remove 28L PDIP 300mil Issue Date Jul. 22,2005 Mar. 10,2006 Mar. 7,2007 Apr. 30,2007 Chiplus reserves the right to change product or without notice. The CS18HS02563 series products are by 8-bits static RAMs fabricated with advanced 8" wafer submicron.