Details, datasheet, quote on part number: TMS29F002
CategoryMemory => Flash => Parallel Flash => 2M
Description262 144 BY 8-bit Flash Memory
CompanyTexas Instruments, Inc.
DatasheetDownload TMS29F002 datasheet


Features, Applications

PIN NOMENCLATURE OE NC VCC VSS WE Address Inputs Data In / Data out Chip Enable Output Enable No Internal Connection Power Supply Ground Write Enable


The 152-bit), 5-V single-supply, programmable read-only memory device that can be electrically erased and reprogrammed. This device is organized x 8 bits, divided into seven sectors: One 16K-byte protected-boot sector Two 8K-byte sectors One 32K-byte sector Three 64K-byte sectors

Any combination of sectors can be marked as read-only or erased. Full chip erasure is also supported. Sector data protection is afforded by methods that can disable any combination of sectors from write or read operations using standard programming equipment. An on-chip state machine provides an on-board algorithm that automatically pre-programs and erases any sector before it automatically programs and verifies program data at any specified address. The command set is compatible with that of the Joint Electronic Device Engineering Council (JEDEC) standards is compatible the warranty, JEDEC 2M-byte erasable Please be aware that an important notice and concerning availability,with standard and use inelectrically critical applications of Texas Instruments semiconductor and disclaimers thereto at the end of thisfeature data sheet. programmable read-only memoryproducts (EEPROM) command set.appears A suspend/resume allows access to

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

Single Power Supply Supports 5-V 10% Read/Write Operation Organization:. By 8 Bits Array-Blocking Architecture ­ One 16K-Byte Protected-Boot Sector ­ Two 8K-Byte Parameter-Sectors ­ One 32K-Byte Sector ­ Three 64K-Byte Sectors ­ Any Combination of Sectors Can Be Erased. Supports Full-Chip Erase ­ Any Combination of Sectors Can Be Marked as Read-Only Boot-Code Sector Architecture T = Top Sector B = Bottom Sector Protection ­ Hardware Protection Method That Disables Any Combination of Sectors From Write or Erase Operations Using Standard Programming Equipment Embedded Program/Erase Algorithms ­ Automatically Pre-Programs and Erases Any Sector ­ Automatically Programs and Verifies the Program Data at Specified Address JEDEC Standards ­ Compatible With JEDEC Byte Pinouts ­ Compatible With JEDEC EEPROM Command Set Fully Automated On-Chip Erase and Program Operations

100 000 Program/Erase Cycles Low Power Dissipation Low Current Consumption ­ 40-mA Typical Active Read ­ 60-mA Typical Program/Erase Current ­ Less Than 100-µA Standby Current All Inputs/Outputs TTL-Compatible Erase Suspend/Resume ­ Supports Reading Data From, or Programming Data to, a Sector Not Being Erased 40-Pin Thin Small Outline Package (TSOP) (DCD Suffix) Detection Of Program/Erase Operation ­ Data Polling and Toggle Bit Feature of Program/Erase Cycle Completion High-Speed Data Access at 5-V VCC ­ 70 Commercial. ­ 80 Extended. to 85°C

unaltered memory blocks during a section-erase operation. All outputs of this device are TTL-compatible. Additionally, an erase/suspend/resume feature supports reading data from, or programming data to, a sector that is not being erased. Device operations are selected by writing JEDEC-standard commands into the command register using standard microprocessor write timings. The command register acts as an input to an internal-state machine which interprets the commands, controls the erase and programming operations, outputs the status of the device, outputs data stored in the device, and outputs the device algorithm-selection code. On initial power up, the device defaults to the read mode. The device has low power dissipation with a 40-mA active read for the byte mode, 60-mA typical program/erase current mode, and less than 100-mA standby current. These devices are offered with 70 and 80 ns access times. Table 1 and Table 2 show the sector-address ranges. The TMS29F002T/B is offered a 40-pin (DCD suffix) thin small-outline package.

Temperature Range L = Commercial E = Extended to 85°C) Package Type DCD = Thin Small-Outline Package Program/Erase Endurance 100 000 cyc 10 000 cyc Speed Option 80 ns Boot Code Selection Architecture T = Top Sector B = Bottom Sector Device Number / Description xxx 002 2M bit

This symbol is in accordance with ANSI / IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the FM package.


Some Part number from the same manufacture Texas Instruments, Inc.
TMS29F002R 262 144 BY 8-bit Flash Memory
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TMS29F002RT-10BFML ti TMS29F002RT, 262 144 BY 8-Bit Boot Block Flash Memory
TMS29F010 131 072 BY 8-bit Flash Memory
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TMS29LF040 ti TMS29LF040, 4 194 304-Bit Flash Memory
TMS29LF800B ti TMS29LF800B, 8 388 608-Bit Boot-sector Flash Memo
TMS29LF800T ti TMS29LF800T, 8 388 608-Bit Flash Memories
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