|Category||Semiconductors => Memory => Flash|
|Part family||TMS29LF008T 8 388 608-Bit Boot-Sector Flash Memory|
|Description||ti TMS29LF008T, 8 388 608-Bit Boot-sector Flash Memory|
|Company||Texas Instruments, Inc.|
|Datasheet||Download TMS29LF008T datasheet
|Pin nb||Package type||Ind std||JEDEC code||Package qty||Carrier||Device mark||Width (mm)||Length (mm)||Thick (mm)||Pitch (mm)|
Single Power Supply Supports 2.7-V and 3.6-V Read/Write Operation Organization. By 8 Bits Array Blocking Architecture One 16K-Byte Boot Sector Two 8K-Byte Parameter Sectors One 32K-Byte Sector Fifteen 64K-Byte Sectors Any Combination of Sectors Can Be Erased. Supports Full-Chip Erase Any Combination of Sectors Can Be Marked as Read-Only Boot-Code Sector Architecture T = Top Sector B = Bottom Sector Protection Hardware Protection Method That Disables Any Combination of Sectors From Write or Erase Operations Using Standard Programming Equipment Embedded Program/Erase Algorithms Automatically Pre-Programs and Erases Any Sector Automatically Programs and Verifies the Program Data at Specified Address JEDEC Standards Compatible With JEDEC Byte Pinouts Compatible With JEDEC EEPROM Command Set Fully Automated On-Chip Erase and Program Operations 100 000 Program/Erase Cycles Low Power Dissipation Low Current Consumption 20-mA Typical Active Read for Byte Mode 30-mA Typical Program / Erase Current Less Than 60-µA Standby Current µA in Deep Power-Down Mode
PIN NOMENCLATURE OE NC RESET / BY VCC VSS WE Address Inputs Data In / Data out Chip Enable Output Enable No Internal Connection Reset / Deep Power Down Ready / Busy Output Power Supply Ground Write Enable
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
All Inputs/Outputs TTL-Compatible Erase Suspend/Resume Supports Reading Data From, or Programming Data to, a Sector Not Being Erased Hardware-Reset Pin Initializes the Internal-State Machine to the Read Operation 40-Pin Thin Small-Outline Package (TSOP) (DCD Suffix) Detection Of Program/Erase Operation Data Polling and Toggle Bit Feature of Program/Erase Cycle Completion Hardware Method for Detection of Program/Erase Cycle Completion Through Ready/Busy (RY/BY) Output Pin High-Speed Data Access at 3.3-V VCC 10% at Three Temperature Ranges 90 ns Commercial. 100 ns Extended. 120 ns Automotive. to 125°Cdescription
The 608-bit), 3-V single-supply, programmable read-only memory device that can be electrically erased and reprogrammed. This device is organized by 8 bits, divided into 19 sectors: One 16K-byte boot sector Two 8K-byte sectors One 32K-byte sector Fifteen 64K-byte sectors
Any combination of sectors can be marked as read-only or erased. Full-chip erasure is also supported. Sector data protection is afforded by methods that can disable any combination of sectors from write or read operations using standard programming equipment. An on-chip state machine controls the program and erase operations by providing an on-board algorithm that automatically pre-programs and erases any sector before it automatically programs and verifies program data at any specified address. The command set is compatible with that of the Joint Electronic Device Engineering Council (JEDEC) standards and is compatible with the JEDEC 8M-bit electrically erasable, programmable read-only memory (EEPROM) command set. A suspend/resume feature allows access to unaltered memory blocks during a section-erase operation. All outputs of this device are TTL-compatible. Additionally, an erase/suspend/resume feature supports reading data from, or programming data to, a sector that is not being erased.
Device operations are selected by writing JEDEC-standard commands into the command register using standard microprocessor write timings. The command register acts as an input to an internal-state machine which interprets the commands, controls the erase and programming operations, outputs the status of the device, outputs the data stored in the device, and outputs the device algorithm-selection code. On initial power up, the device defaults to the read mode. A hardware-reset pin initializes the internal-state machine to the read operation. The device has low power dissipation with a 20-mA active read for the byte mode, 30-mA typical program/erase current mode, and less than 60-mA standby current with a 5-mA deep-power-down mode. These devices are offered with 90-, 100-, and 120-ns access times. Table 1 and Table 2 show the sector-address ranges. The TMS29LF008T/B is offered a 40-pin thin small-outline package (TSOP) (DCD suffix).
90 C DCD L Temperature Range Designator L = Commercial E = Extended Q = Automotive to 125°C) Package Designator DCD = 40-Pin Plastic Dual Small-Outline Package
Boot Code Selection Architecture T = Top Sector B = Bottom Sector Device Number / Description 8M Bits
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IDT72215 : 512 X 18 Syncfifo, 5.0V. x 18-bit organization array x 18-bit organization array x 18-bit organization array x 18-bit organization array x 18-bit organization array 10 ns read/write cycle time Empty and Full flags signal FIFO status Easily expandable in depth and width Asynchronous or coincident read and write clocks Programmable Almost-Empty and Almost-Full flags with default.
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