Details, datasheet, quote on part number: TMS29LF040-10C5DDL
PartTMS29LF040-10C5DDL
CategorySemiconductors => Memory => Flash
Part familyTMS29LF040 4 194 304-Bit Flash Memory
Descriptionti TMS29LF040, 4 194 304-Bit Flash Memory
CompanyTexas Instruments, Inc.
StatusOBSOLETE
ROHSNot Compliant
SampleNo
DatasheetDownload TMS29LF040-10C5DDL datasheet
  
  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
32DD 818.421.1

 

Features, Applications

Single Power Supply 10% See TMS29F040 Data sheet (Literature Number SMJS820) Organization. By 8 Bits Eight Equal Sectors of 64K Bytes Any Combination of Sectors Can Be Erased Any Combination of Sectors Can Be Marked as Read-Only Compatible With JEDEC Electrically Erasable Programmable Read-Only Memory (EEPROM) Command Set Fully Automated On-Chip Erase and Byte-Program Operations 100 000 Program / Erase Cycles Erase-Suspend/ Erase-Resume Operation Compatible With JEDEC Byte-Wide Pinouts Low-Current Consumption Active Read. 20 mA Typical Active Program / Erase. 30 mA Typical All Inputs/Outputs CMOS-Compatible Only

PIN NOMENCLATURE E G VCC VSS W Address Inputs (programming) / Outputs Chip Enable Output Enable Power Supply Ground Write Enable

description

The TMS29LF040 and TMS29VF040 are 194 304-bit), low-voltage, single-supply, programmable read-only memories that can be erased electrically and reprogrammed. These devices are organized as eight independent 64K-byte sectors and are offered with access times between 80 ns and 150 ns. An on-chip state machine controls the program and erase operations. The embedded-byte program and sector/ chip-erase functions are fully automatic. The command set is compatible with that of JEDEC 4M-bit EEPROMs. A suspend / resume feature allows access to unaltered memory sectors during a sector-erase operation. Data protection of any sector combination is accomplished using a hardware sector-protection feature. Device operations are selected by writing JEDEC-standard commands into the command register using standard microprocessor-write timings. The command register acts as input to an internal state machine that interprets the commands, controls the erase and programming operations, and outputs the status of the device, the data stored in the device, and the device algorithm-selection code. On initial power-up operation, the device defaults to the read mode. The TMS29xF040 is offered 14 mm thin small-outline package (DBW suffix), 20 mm thin small-outline package (DD suffix), and a 32-pin plastic leaded chip carrier (FM suffix) using mm (50-mil) lead pitch.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Temperature Range Designator L = Commercial E = Extended to 85C) Package Designator DD = Thin Small-Outline Package 20 mm) DBW = Thin Small-Outline Package 14 mm) FM = Plastic Leaded Chip Carrier Program / Erase Endurance 100 000 Cycles Speed Designator 150 ns

VCC Range Designator 0.3 V VCC (Low Voltage) 3.6 V VCC (Very Low Voltage)
Command Register W Erase-Voltage Generator State Control Program-Voltage Generator Data Latch

 

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