Details, datasheet, quote on part number: TMS320
CategoryDSPs (Digital Signal Processors) => 320 Family
Title320 Family
DescriptionFloating-point Digital Signal Processors
CompanyTexas Instruments, Inc.
DatasheetDownload TMS320 datasheet
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Features, Applications

New TMS320C6712 DSP: 100MHz, 600 MFLOPS, U.S. (100Ku) TMS320VC33 DSP: 60 MHz, 120 MFLOPS, U.S. (100Ku) TMS320C6711 DSP: 900 MFLOPS with dual-level cache architecture TMS320C6701 DSP: the highest performance floating-point DSP in production today delivers to 1 GFLOPS TMS320C67xTM DSPs are code compatible with TMS320C62xTM fixed-point DSPs Industry's most advanced C compiler achieves greater than 80 percent of the performance of hand-coded assembly New TMS320C6711 DSP Starter Kit (DSK) for only U.S. $295.00 enables easy prototyping of TMS320C6000TM DSP-based designs (Available 4Q00)

Application designers now have the greatest range of price and performance options with floating-point digital signal processors (DSPs) from Texas Instruments. TMS320C67xTM DSPs are the industry's most powerful floating-point processors, and TMS320C3xTM DSPs provide incredible performance, precision and dynamic range. These processors are available at a number of price points so developers can select the device that best meets the needs of target applications.

The TI Floating-Point DSP Advantage TI floating-point DSPs raise the bar in performance, set new levels in cost efficiency, and offer low power dissipation--energizing existing products and supporting the development of next-generation applications. Several features of TI's floating-point DSPs make them attractive for applications that require a larger dynamic range and a higher level of precision than offered by typical 16-bit fixed-point devices. For example, a 32-bit

word-width enables high fidelity audio systems to produce more life-like sound. Graphics and imaging systems need the full 32-bits to achieve greater resolution and more realistic visuals. In addition, the DSPs' substantial processing power provides higher frame rates and additional polygon manipulations that further enhance image sharpness and quality. Motion control, automotive, robotics, instrumentation, military and voice/speech applications similarly benefit from the extra precision and high performance of TI floating-point DSPs.

TI provides application designers the largest assortment of DSP floating-point price and performance options. TI leads the way in floating-point DSP technology and continues to build on its leadership position--as it has for more than 12 years.

Unparalleled Performance with VelociTI TM Architecture All TMS320C6000TM DSPs are based on the same CPU core, featuring VelociTITM, an advanced very long instruction word (VLIW) architecture designed to achieve high performance through increased instructionlevel parallelism. TI achieves breakthrough performance by adding floating-point instructions to six of the C6000 DSP architecture's eight functional units. The eight functional units, including two multipliers and six arithmetic units, are highly orthogonal, providing the

compiler and Assembly Optimizer with many execution resources. Eight 32-bit RISClike instructions are fetched by the CPU each cycle. The VelociTI instruction packing features allow these eight instructions to be executed in parallel, in serial, or in parallel/serial combinations. This optimized scheme enables significant reductions in code size, program fetches and power consumption. Unified Architecture Provides Code Compatibility With the same VelociTITM core, TI's C67xTM DSPs are code and

pin-for-pin compatible with C62xTM fixed-point DSPs. The C67x DSP instruction set is a superset of that for the C62x devices. This allows developers to take advantage of the ease-of-use of floating-point by prototyping on the C6711 DSP, and then porting their code to the fixed-point C6211 DSP for reduced production costs. Together with the ease of a single development platform, this code-transfer capability between fixedand floating-point DSPs results in significant savings in development, resource and manufacturing costs.

DAT/PRO (address reach) 52 Mbytes Ext Memory Interface ­ 32-bit Cycle (ns) MFLOPS 6 1000 Host Port 16-bit Packaging Interface

Voltage 3.3V I/O; 1.9V Core 3.3V I/O; 1.8V Core 3.3V I/O; 1.8V Core 3.3V I/O; 1.8V Core 3.3V I/O; 1.8V Core

# denotes bootloader - the TMS320C30 is available in three speed grades: 30 MHz , 40 MHz, and 50 MHz (shown). - the TMS320C31 is available in four speed grades: 40 MHz , 50 MHz, 60 MHz (shown) and the new 80 MHz (shown). - the TMS320C32 is available in three speed grades: 40 MHz , 50 MHz, and 60 MHz (shown).

Program Fetch Instruction Dispatch Instruction Decode Data Path 1 A Register File Data Path 2 B Register File Emulation S2 L2 Interrupt Control Registers Control Logic Test

L Unit: 32/40-bit fixed-point arithmetic and compare operations 32/64-bit floating-point arithmetic and compare operations (IEEE single and double precision) 32-bit fixed-point logical operations Fixed/floating-point conversions to 32-bit floating-point conversions S Unit: 32-bit fixed-point arithmetic operations 32/40-bit shifts and 32-bit bit-field operations Branching and constant generation 32/64-bit floating-point reciprocal, absolute value, compares and 1/sqrt operations to 64-bit floating-point conversions M Unit: x 16-bit fixed-point multiplies x 32-bit fixed-point multiplies x 32-bit single-precision floating-point multiplies x 64-bit double-precision floating-point multiplies D Unit: 32-bit add, subtract, linear and circular address calculation 8/16/32/64-bit loads 8/16/32-bit stores

Key Features of the C67x TM DSP Core Load store architecture with 32 general-purpose registers, each 32-bit IEEE floating-point format - 1 GFLOPS single precision - 420 MFLOPS double precision--hardware supported CPU - Dual data path - 8 functional units (4 Floating & Fixed-Point ALUs, 2 Fixed-Point ALUs, and 2 Multipliers) 8, 32-bit instructions per cycle 32-bit address range Additional integer multiply instructions not available on the C62xTM core - 32-bit multiply Integer instruction features - Data byte addressable 16-, 32-bit data) - 8 bits overflow protection - Saturation - Bit field extract, set, clear - Bit counting - Instruction packing reduces code size - All instructions conditional

Instruction Set Features Hardware support for IEEE single-precision instructions Hardware support for IEEE double-precision instructions Byte-addressable 16-, 32-bit Data) 8-bit overflow protection Saturation Bit-field extract, set, clear Bit-counting Normalization 100% Conditional instructions through five registers B0, B1 and B2) Low power modes Comprehensive Development Support Ultra-efficient C compiler, ANSI C, and C++ Industry's first assembly optimizer Code Composer debugger Code Composer simulator Code Composer StudioTM IDE integrated DSP development environment: - Real-time analysis and debug capabilities using RTDXTM technology and DSP/BIOS - Standard application program interfaces (APIs)

Development Support Tools C67xTM evaluation module (EVM) is available to assist in development For only $295, developers can start today to develop on the TMS320C6711 DSP Development Kit (DSK) enabling easy and inexpensive benchmarking and prototyping of C6000 DSP-based designs.


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