|Category||DSPs (Digital Signal Processors) => TMS320 Family->TMS320C5X Fixed Point DSP|
|Title||TMS320 Family->TMS320C5X Fixed Point DSP|
|Description||ti TMS320BC52, Digital Signal Processors|
|Company||Texas Instruments, Inc.|
|Datasheet||Download TMS320BC52PJ datasheet
Powerful 16-Bit TMS320C5x CPU 25-, 35-, and 50-ns Single-Cycle Instruction Execution Time for 5-V Operation 25-, 40-, and 50-ns Single-Cycle Instruction Execution Time for 3-V Operation Single-Cycle × 16-Bit Multiply/Add × 16-Bit Maximum Addressable External Memory Space (64K Program, 64K Data, 64K I/O, and 32K Global) × 16-Bit Single-Access On-Chip Program ROM × 16-Bit Single-Access On-Chip Program / Data RAM (SARAM) 1K Dual-Access On-Chip Program / Data RAM (DARAM) Full-Duplex Synchronous Serial Port for Coder/Decoder Interface Time-Division-Multiplexed (TDM) Serial Port Hardware or Software Wait-State Generation Capability On-Chip Timer for Control Operations Repeat Instructions for Efficient Use of Program Space Buffered Serial Port Host Port Interface
Multiple Phase-Locked Loop (PLL) Clocking Options Depending on Device) Block Moves for Data/Program Management On-Chip Scan-Based Emulation Logic Boundary Scan Five Packaging Options 100-Pin Quad Flat Package (PJ Suffix) 100-Pin Thin Quad Flat Package (PZ Suffix) 128-Pin Thin Quad Flat Package (PBK Suffix) 132-Pin Quad Flat Package (PQ Suffix) 144-Pin Thin Quad Flat Package (PGE Suffix) Low Power Dissipation and Power-Down Modes: mA / MIP) V, 40-MHz Clock (Average) mA / MIP) V, 40-MHz Clock (Average) V, 40-MHz Clock (IDLE1 Mode) V, 40-MHz Clock (IDLE2 Mode) 5 V, Clocks Off (IDLE2 Mode) High-Performance Static CMOS Technology IEEE Standard 1149.1 Test-Access Port (JTAG)description
The TMS320C5x generation of the Texas Instruments (TITM ) TMS320 digital signal processors (DSPs) is fabricated with static CMOS integrated circuit technology; the architectural design is based upon that of an earlier TI DSP, the TMS320C25. The combination of advanced Harvard architecture, on-chip peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational flexibility and speed of the 'C5x devices. They execute to 50 million instructions per second (MIPS). The 'C5x devices offer these advantages:
Enhanced TMS320 architectural design for increased performance and versatility Modular architectural design for fast development of spin-off devices Advanced integrated-circuit processing technology for increased performance Upward-compatible source code (source code for 'C1x and 'C2x DSPs is upward compatible with 'C5x DSPs.) Enhanced TMS320 instruction set for faster algorithms and for optimized high-level language operation New static-design techniques for minimizing power consumption and maximizing radiation tolerance
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. is a trademark of Texas Instruments Incorporated. IEEE Standard 1149.11990, IEEE Standard Test-Access Port and Boundary-Scan Architecture References 'C5x in this document include both TMS320C5x and TMS320LC5x devices unless specified otherwise.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Table 1 provides a comparison of the devices in the 'C5x generation. It shows the capacity of on-chip RAM and ROM memories, number of serial and parallel I/O ports, execution time of one machine cycle, and type of package with total pin count. Table 1. Characteristics of the 'C5x Processors
ON-CHIP MEMORY (16-BIT WORDS) TMS320 DEVICES DARAM DATA TMS320LC57 TMS320C57S DATA + PROG SARAM DATA + PROG 3K 6K ROM PROG 32K 2K§ I/O PORTS SERIAL PARALLEL 64K + HPI 64K + HPI 64K + HPI POWER SUPPLY (V) CYCLE TIME (ns) PACKAGE TYPE QFP 132 pin 132 pin 100/132 pin 100/132 pin 100 pin 100 pin 132 pin 132 pin 100 pin 100 pin 100 pin 128 pin 144 pin 144 pin
6K 2K§ Sixteen of the 64K parallel I/O ports are memory mapped. QFP = Quad flatpack § ROM boot loader available ¶ TDM serial port not available # Includes auto-buffered serial port (BSP) but TDM serial port not available HPI = Host port interface
TCLKR TFSR / TADD CLKX TCLKX TOUT VSSC EMU1/ OFF NC VDDD D14 D15 MP/ MC VSSI TRST IAQ VDDC BIO HOLD READY RS
NC VDDI IACK CLKOUT1 XF HOLDA TDX DX TFSX / TFRM FSX CLKMD2 VSSI TDO VDDC X2 / CLKIN CLKIN2 BR STRB DS NC VSSC NC
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