|Category||Semiconductors => Processors => Digital Signal Processors => C6000 DSP => Other C6000 DSP|
|Part family||TMS320C6455 Fixed-Point Digital Signal Processor|
|Description||Fixed-Point Digital Signal Processor 697-FCBGA 0 to 90|
|Company||Texas Instruments, Inc.|
|Datasheet||Download TMS320C6455 datasheet
|Approx. Price (US$)||171.56 | 1ku|
|Pin nb||Package type||Ind std||JEDEC code||Package qty||Carrier||Device mark||Width (mm)||Length (mm)||Thick (mm)||Pitch (mm)|
|697||CTZ||44||JEDEC TRAY (5+1)||1GHZ||24||24||2.65|
|• Implementing Serial Rapid I/O PCB layout on a TMS320C6455 Hardware Design (Rev. A)
This application report contains implementation instructions for the Serial Rapid I/O (SRIO) interface on the TMS320C6455 DSP device. The approach to specifying interface timing and physical requirements for the SRIO interface is quite different than previ | Doc
|• Ultrasound Scan Conversion on TI's C64x+ DSPs
One of the recent significant developments in ultrasound is the emergence of portable and handheld ultrasound machines and their rapid acceptance in the market place.Because of their power efficiency and high performance, digital signal processor (DSP) bas | Doc
|• EDMA v3.0 (EDMA3) Migration Guide for TMS320C645x DSP
The TMS320C645x devices introduce a newly designed Enhanced Direct Memory Access (EDMA3). The EDMA3 has many new features that improve system performance and enhance debugging capabilities. This document summarizes the key differences between EDMA3 on the | Doc
|• Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A)
This application report motivates the way the DDR high-speed timing requirements are now going to be communicated to system designers. The traditional method of using data sheet parameters and simulation models is tedious. The system designer uses this inf | Doc
|• TMS320C6455 Design Guide and Comparisons to TMS320C6416T (Rev. A)
This document describes system design considerations for the TMS320C6455 (C6455). It also gives comparisons to designing with the TMS320C6416T (C6416T) for those familiar with that device. The objective of this document is to cover system design considerat | Doc
|• Preparing an C645x application for I2C Boot Load
This application report describes how to prepare a C645x application for the I2C boot load process.The enclosed .zip archive contains all utilities and examples necessary to build a test application, program it into DSK6455's I2C ROM, change the boot mode | Doc
|• TMS320C6455 to TMS320C6474 Migration Guide
The TMS320C6455 fixed-point digital signal processor (DSP) and the TMS320C6474 communications infrastructure DSP are two of Texas Instrumentsâ€™ high-performance DSP processors, each offering high-speed DSP processing, large internal memories, a rich set o | Doc
|• Introduction to TMS320C6000 DSP Optimization
The TMS320C6000â„˘ Digital Signal Processors (DSPs) have many architectural advantages that make them ideal for computation-intensive real-time applications. However, to fully leverage the architectural features that C6000â„˘ processors offer, code optimiz | Doc
|• TMS320C6455/C6454 Power Consumption Summary (Rev. B)
This application report discusses the power consumption of the Texas Instruments TMS320C6455 and TMS320C6454 digital signal processor (DSPs). The power consumption on the C645x devices is highly application-dependent, therefore, a power spreadsheet that pr | Doc
|• EDMA v2.0 to EDMA v3.0 (EDMA3) Migration Guide (Rev. A)
This application report summarizes the key differences between the enhanced direct memory access (EDMA3) used on C64x+â„˘ DSP devices and the EDMA2 used on TMS320C64xâ„˘ DSP devices, and provides guidance for migrating from EDMA2 to EDMA3. | Doc
|• Common Object File Format (COFF) | Doc|
|• Tuning VCP2 and TCP2 Bit Error Rate Performance
In most customer applications, a high level of decoding bit error rate (BER) performance is required. Since Convolutional codes and Turbo codes are widely used in wireless communication systems, TI DSPs integrate two high-performance embedded coprocessors | Doc
|• Implementing DDR2 PCB Layout on the TMS320C6455/C6454 (Rev. E)
This application report contains implementation instructions for the DDR2 interface contained on the TMS320C6454/5 digital signal processor (DSP) device. The approach to specifying interface timing for the DDR2 interface is quite different than on previous | Doc
|• SW Operation of Gigabit Ethernet Media Access Controller on TMS320C645x DSP
The TMS645x devices provide an efficient interface between the DSP core processor and the network via a high performance Gigabit Ethernet Media Access Controller (EMAC), supporting four Media Independent Interfaces to the physical layer device (PHY).This a | Doc
|• TMS320C64x to TMS320C64x+ CPU Migration Guide (Rev. A)
This document describes migration from the Texas Instruments TMS320C64xâ„˘ digital signal processor (DSP) to the TMS320C64x+â„˘ DSP. The objective of this document is to indicate differences between the two cores and to briefly describe new features. Funct | Doc
|• TMS320C64x+ Megamodule
The C64X+ Megamodule supports a wide variety of internal memory configurations by allowing the L1 program and data memory (L1P and L1D) to set as cache only, SRAM only, or a mixture of cache and SRAM. In addition, the C64x+ Megamodule provides new system f | Doc
|• Error Detection and Correction Mechanism of TMS320C64x+/C674x (Rev. A)
This application report describes the error detection and correction mechanism of the C64x+/C674x megamodule L1P and L2 memories implemented on some devices. Depending on the type of application, these mechanisms are used to either provide diagnostic measu | Doc
|TMDSEMU560V2STM-U: XDS560v2 System Trace USB Debug Probe|
|XDS560TRACE: XDS560 Trace Emulator|
|TMDSEVM6472: TMS320C6472 Evaluation Module|
|TMDXEVM6452: C6452 DSP Evaluation Module|
|TMDSDSK6455: TMS320C6455 DSP Starter Kit (DSK)|
|TMDSEMU200-U: XDS200 USB Debug Probe|
|TMDSEMU560V2STM-UE: XDS560v2 System Trace USB & Ethernet Debug Probe|
EDMA Controller (64 Independent Channels) Four 1x Serial RapidIO® Links (or One 4x), v1.2 Compliant 2.5-, 3.125-Gbps Link Rates Message Passing, DirectIO Support, Error Management Extensions, and Congestion Control IEEE 1149.6 Compliant I/Os 32-/16-Bit Host-Port Interface (HPI) 32-Bit/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.3 One Inter-Integrated Circuit (I2C) Bus Two Multichannel Buffered Serial Ports (McBSPs) 10/100/1000 Mb/s Ethernet MAC (EMAC) IEEE 802.3 Compliant Supports Multiple Media Independent Interfaces (MII, GMII, RMII, and RGMII) 8 Independent Transmit (TX) and 8 Independent Received (RX) Channels Two 64-Bit General-Purpose Timers, Configurable as Four 32-Bit Timers Universal Test and Operations PHY Interface for ATM (UTOPIA) UTOPIA Level 2 Slave ATM Controller 8-Bit Transmit and Receive Operations to 50 MHz per Direction User-Defined Cell Format to 64 Bytes 16 General-Purpose I/O (GPIO) Pins PLL1 and PLL1 Controller PLL2 Dedicated for DDR2 EMIF and EMAC IEEE-1149.1 (JTAG) Boundary-Scan-Compatible 697-Pin Ball Grid Array (BGA) Package (ZTZ Suffix), 0.8-mm Ball Pitch 0.09-µm/7-Level Cu Metal Process (CMOS) 1.5-, 1.2-V I/Os, 1.2-V Internal
High-Performance Fixed-Point DSP 1.17-, 1-ns Instruction Cycle Time 720-, 850-MHz and 1-GHz Clock Rate Eight 32-Bit Instructions/Cycle MIPS MMACS (16 Bits) Commercial Temperature 90°C] TMS320C64x+TM DSP Core Dedicated SPLOOP Instruction Compact Instructions (32-/16-Bit) Instruction Set Enhancements Exception Handling TMS320C64x+ Megamodule L1/L2 Memory Architecture: (32K-Byte) L1P Program Cache [Direct Mapped] (32K-Byte) L1D Data Cache [2-Way Set-Associative] (2048K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation] Enhanced Viterbi Decoder Coprocessor (VCP2) Supports Over 694 7.95-Kbps AMR Programmable Code Parameters Enhanced Turbo Decoder Coprocessor (TCP2) Supports up to Eight 3GPP (6 Iterations) Programmable Turbo Code and Decoding Parameters Endianess: Little Endian, Big Endian 64-Bit/133-MHz EMIFA Glueless Interface to Asynchronous Memories (SRAM, Flash, and EPROM) Glueless Interface to Synchronous Memories (SBSRAM and ZBT SRAM) Supports Interface to Standard Sync Devices Sync or Async Interface to Custom Logic (FPGA, CPLD, ASICs, etc.) 32M-Byte Total Addressable External Memory Space (8MB per CE space) 32-Bit DDR2 EMIF (DDR2-500 SDRAM)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
The TMS320C6455 devices are designed for a package temperature range to +90°C (commercial temperature range).ZTZ 697-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW )
NOTE: The ZTZ mechanical package designator represents the version of the GTZ package with lead-free balls. For more detailed information, see the Mechanical Data section of this document.Description
The TMS320C64x+TM DSPs (including the TMS320C6455 device) are the highest-performance fixed-point DSP generation in the TMS320C6000TM DSP platform. The C6455 device is based on the third-generation high-performance, advanced VelociTITM very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for applications including video and telecom infrastructures, imaging/medical, and wireless infrastructure (WI). The C64x+TM devices are upward code-compatible from previous devices that are part of the C6000TM DSP platform. Based on 90-nm process technology and with performance to 8000 million instructions per second (MIPS) [or 8000 16-bit MMACs per cycle] at a clock rate of 1 GHz, the C6455 device offers cost-effective solutions to high-performance DSP programming challenges. The C6455 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or.M units. Each C64x+.M unit doubles the multiply throughout versus the C64x core by performing four x 16-bit multiply-accumulates (MACs) every clock cycle. Thus, eight x 16-bit MACs can be executed every cycle on the C64x+ core. a 1-GHz clock rate, this means 8000 16-bit MMACs can occur every second. Moreover, each multiplier on the C64x+ core can compute one x 32-bit MAC or four x 8-bit MACs every clock cycle.
The C6455 device has two high-performance embedded coprocessors [enhanced Viterbi Decoder Coprocessor (VCP2) and enhanced Turbo Decoder Coprocessor (TCP2)] that significantly speed up channel-decoding operations on-chip. The VCP2 operating at CPU clock divided-by-3 can decode over 694 7.95-Kbps adaptive multi-rate (AMR) = 1/3] voice channels. The VCP2 supports constraint lengths K and 9, rates R and 1/5 and flexible polynomials, while generating hard decisions or soft decisions. The TCP2 operating at CPU clock divided-by-3 can decode up to fifty 384-Kbps or eight 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP2 implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the VCP2/TCP2 and the CPU are carried out through the EDMA controller. The C6455 DSP integrates a large amount of on-chip memory organized as a two-level memory system. The level-1 (L1) program and data memories on the C6455 device are 32KB each. This memory can be configured as mapped RAM, cache, or some combination of the two. When configured as cache, L1 program is a direct mapped cache where as L1 data is a two-way set associative cache. The level 2 (L2) memory is shared between program and data space and 2MB in size. L2 memory can also be configured as mapped RAM, cache, or some combination of the two. The C64x+ Megamodule also has a 32-bit peripheral configuration (CFG) port, an internal DMA (IDMA) controller, a system component with reset/boot control, interrupt/exception control, a power-down control, and a free-running 32-bit timer for time stamp. The C6455 device includes Serial RapidIO®. This high bandwidth peripheral dramatically improves system performance and reduces system cost for applications that include multiple DSPs on a board, such as video and telecom infrastructures and medical/imaging. The peripheral set also includes: an inter-integrated circuit bus module (I2C); two multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port; two 64-bit general-purpose timers (also configurable as four 32-bit timers); a user-configurable or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output port (GPIO) with programmable interrupt/event generation modes; an 10/100/1000 Ethernet media access controller (EMAC), which provides an efficient interface between the C6455 DSP core processor and the network; a management data input/output (MDIO) module (also part of the EMAC) that continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system; a glueless external memory interface (64-bit EMIFA), which is capable of interfacing to synchronous and asynchronous peripherals; and 32-bit DDR2 SDRAM interface. The I2C ports on the C6455 allow the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices. The C6455 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.
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