|Category||DSPs (Digital Signal Processors) => 320 Family|
|Description||Cpu, Memory And Peripheral System|
|Company||Texas Instruments, Inc.|
|Datasheet||Download TMS320C64XDSP datasheet
The world's highest performance DSP core, scalable to 1.1 GHz and beyond. New two-level cache supports the high-performance C64xTM DSP core. Enhanced Direct Memory Access (DMA) provides more than GB of sustained bandwidth. Synchronous External Memory Interfaces (EMIFs) and Host Interface provide over GB of bandwidth. Complete software compatibility with the programmable TMS320C6000TM DSP platform.The World's Fastest DSPs Complemented by a HighPerformance Memory and Peripheral System
The TMS320C64xTM DSP core scales operating speeds beyond 1 GHz and achieves 10X performance improvements over the industry's previous DSP performance leader, the TMS320C62xTM DSP. Chips in development couple this processing performance with a new memory and peripheral system designed to accelerate realtime throughput for higher system performance. The C64xTM DSP core provides greater overall efficiency for demanding applications such as digital subscriber line
access multiplexers (DSLAMs), broadband video transcoding, streaming video servers, highspeed raster image processing (RIP) engines and network cameras. Full object code compatibility with existing C62xTM DSPs allows system developers to work on next-generation C64xTM DSP designs today. Highlights of the C64xTM DSP Core VelociTI.2TM architecture extensions with new instructions to accelerate performance in key applications Increased parallelism with dual 16-bit or quad 8-bit operations, and two x 16 bit multiplies or four x 8 bit multiplies
Packed data processing for formatting data within registers so that instructions can operate directly Initial devices are expected to operate - 800 MHz with scalable performance to over 1.1 GHz Improved orthogonality with frequently used instructions available in more functional units Double the bandwidth resulting from more registers, wider load/store data paths and enlarged 2-level cache Completely software compatible with C62x DSPs
TMS320C64xTM DSP Core Instruction Fetch Instruction Dispatch Instruction Decode Data Path 1 Register File A Control Registers Interrupt Control In-Circuit Emulation Data Path 2 Register File BMcBSP 0 McBSP 1 McBSP 2 Timer 0 Timer 1 Timer 2 Power Down Logic
The C64xTM DSP core couples its processing performance with a new memory and peripheral system designed to accelerate real-time throughput for higher system performance.
TMS320C64xTM DSP L1/L2 Cache A New Memory and Peripheral System That Measures Up The new C64xTM DSP memory and peripheral system includes a variety of features designed to help developers maximize the many performance advantages of the C64x DSP core:
The two-level cache has been scaled for initial implementation to support the high performance of the core, with 16 Kbytes each in Level 1 data and Level 1 program caches and 128 Kbytes in the unified Level 2 cache. For applications that require greater data determinism, the four associative sets or "ways" of the Level 2 cache can be redefined individually as blocks of memory with fixed addressing.The C64xTM DSP L1/L2 cache sustains core performance at high clock rates.
A 32-channel DMA controller with a highly efficient transfer engine provides more than 2 GB/sec of sustained bandwidth, resulting in faster system performance. Thirty-two channels can be programmed to perform one or more of these tasks in the background of core program execution. Channels can be configured to run continuously throughout the device's entire operation, with only an initial configuration required. Each independently synchronized channel has a dedicated programmable parameter set. The user can configure address modification and stride independently for source and destination. Each channel can be configured to perform fixed, one-dimensional or two-dimensional transfers. Two-dimensional transfers allow automatic interleaving and de-interleaving of data streams and buffers, as well as the movement of sections of 2D
images. A total of 85 parameter sets are available and allow sophisticated linking of transfers. This flexibility permits auto-initializing circular buffers and the background movement of complex data structures.
A 64-bit synchronous External Memory Interface (EMIF), a 16-bit secondary EMIF for peripherals, and a 32-bit Host Port Interface provide over GB of bandwidth on initial implementations. The EMIFs can be clocked independently of the CPU, allowing them to support a wide variety of advanced synchronous and asynchronous external memory devices, including PC100 and PC 133 SDRAMs and various synchronous SRAM standards.
entire ST-Bus span of telephony channels. Direct connect to the ST-Bus allows an easy interface to a variety of H.110/100 and T1/E1 framing devices. The highly flexible and programmable framing, clocking, and baud rate of the McBSPs allow direct interface to multiple high performance audio codecs, including those supporting the AC97 and IIS standards.
Three multi-channel buffered serial ports (McBSPs) support a variety of audio and telecom standards. One hundred twenty-eight independently selectable time slots provide full connectivity to an
Scalable to 1.1 GHz The C64x DSP core uses advanced process technologies (0.15 micron for the initial devices, moving to 0.1 micron in the future) plus innovative logic circuit and design methodologies that focus on minimal wire lengths and low gate counts per clock. Compared to traditional approaches, there are only half the switching wires and transistors needed for the same amount of work. As a result, the C64x DSP core can achieve incredibly high performance to 1.1 GHz.MHz MIPS 16-bit MMACs 8-bit MMACs Communications Imaging Code size reduction
Special purpose instructions Special purpose instructions Advanced instruction packing
support for loops on byte or half-word boundaries and the new SUBABS4 instruction. Morphology - The C64x DSP core provides more than 15X the performance for grayscale operations due to the presence of logical instructions in the.D unit, increased parallelism, and greater scheduling flexibility provided by additional registers.
Overall, the C64xTM DSP core, with advanced VelociTI.2TM VLIW architecture extensions, provides ten times the performance of the industry-leading C62xTM DSP core.
Unbeatable Performance The TMS320C6000TM DSP platform's 1st and 2nd generation comparison chart summarizes the performance advantages of the C64xTM DSP core with TI's advanced VelociTI.2TM architecture extensions.
Application Benchmarks Performance benchmarks a 750 MHz C64x DSP core against the industry leading 300 MHz C62xTM DSP core show that the C64x DSP core achieves far better performance than would be expected on the basis of clock rate alone. This is the result of hardware enhancements, plus the increased performance of the C6000TM DSP platform compiler. To view performance benchmarks visit: www.ti.com/sc/c6000benchmarks
increased parallelism for multiply accumulate operations. Reed Solomon Decode The to 12X improvement here results in a large part from use of the new Galois Field Multiply instruction. Viterbi Decode (GSM) This 7X improvement stems from the additional registers available for state variables and the new MAX and MIN instructions. FFT The 5X improvement here results from the dual 16-bit architecture of the C64x DSP core, plus the new Bit Reverse instruction.
Benchmarks of typical routines used in communications applications show that the C64xTM DSP core to 12 times faster than the C62xTM DSP core.
Digital Communications The C64x DSP core achieves performance improvements to 12X the performance of the C62x DSP core on key routines: Filtering The 5X improvement on 16-bit data is largely the result of
Imaging and Video For imaging and video applications, the C64x DSP core achieves improvements to 19X compared to the C62x DSP core on key routines: IDCT This 5X improvement results from the dual 16-bit mathematical capabilities of the C64x DSP core. Motion Estimation The 19X improvement here comes not only from quad 8-bit support, but also from non-aligned load
Benchmarks of typical routines used in imaging and video applications show that the C64xTM DSP core to 19 times faster than the C62xTM DSP core.
|Some Part number from the same manufacture Texas Instruments, Inc.|
|TMS320C6701 Floating-point Digital Signal Processor|
|TMS320C6701GJC Floating-point Digital Signal Processor|
|TMS320C6701GJC150 ti TMS320C6701, Floating-point Digital Signal Processor|
|TMS320C6711 Floating-point Digital Signal Processor|
|TMS320C6711BGFN100 ti TMS320C6711B, Floating-point Digital Signal Processor|
|TMS320C6711CGDP200 ti TMS320C6711C, Floating-point Digital Signal Processor|
|TMS320C6711GFN Floating-point Digital Signal Processor|
|TMS320C6711GFN100 ti TMS320C6711, Floating-point Digital Signal Processor|
|TMS320C6712 Floating-point Digital Signal Processor|
|TMS320C6712C Floating-point Digital Signal Processors|
|TMS320C6712CGDP150 ti TMS320C6712C, Floating-point Digital Signal Processors|
|TMS320C6712GFN100 ti TMS320C6712, Floating-point Digital Signal Processor|
|TMS320C6713 Floating-point Digital Signal Processor.<<<>>>the TMS320C67x DSPS (including The TMS320C6713 And TMS320C6713B Devices) Compose The Floating-point DSP Generation in The TMS320C6000 DSP Platform. The C6713|
|TMS320C6713BGDP225 Floating-point Digital Signal Processor.<<<>>>the TMS320C67x DSPS (including The TMS320C6713 And TMS320C6713B Devices) Compose The Floating-point DSP Generation in The TMS320C6000 DSP Platform. The C6713|
|TMS320C6713GDP225 ti TMS320C6713, Floating-point Digital Signal Processor|
|TMS320C6713GDPA200 Floating-point Digital Signal Processor.<<<>>>the TMS320C67x DSPS (including The TMS320C6713 And TMS320C6713B Devices) Compose The Floating-point DSP Generation in The TMS320C6000 DSP Platform. The C6713|
AD14060 : 480-MFLOP, Quad DSP, 5v, CQFP Package. PERFORMANCE ADSP-21060 Core Processor 4) 480 MFLOPS Peak, 320 MFLOPS Sustained 25 ns Instruction Rate, Single-Cycle Instruction ExecutionEach of Four Processors 16 Mbit Shared SRAM (Internal to SHARCs) 4 Gigawords Addressable Off-Module Memory Twelve 40 Mbyte/s Link Ports (Three per SHARC) Four 40 Mbit/s Independent Serial Ports (One from Each SHARC).
ADMCF328 : 28-Lead DashDSP Flash Memory Mixed Signal DSP With 5 Analog Input Channels Plus 1 Dedicated Isense Input.
ADSP-2184N : 16-Bit, 80MIPS, 1.8V, 2 Serial Ports, Host Port, 20KB RAM. PERFORMANCE 12.5 ns Instruction Cycle Time @1.8 V (Internal), 80 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 200 CLKIN Cycle Recovery from.
DSP56858FV120 : DSP56800E. 16-Bit Digital Signal Processor. 120 MIPS x 16-bit Program SRAM x 16-bit Data SRAM x 16-bit Boot ROM Access to 2M words of program memory or 8M data memory Chip Select Logic for glue-less interface to ROM and SRAM Six (6) independent channels of DMA Two (2) Enhanced Synchronous Serial Interfaces (ESSI) Two (2) Serial Communication Interfaces (SCI) Serial Port Interface (SPI) 8-bit.
HMU16JC-45 : . The HMU16 and HMU17 are high speed, low power CMOS x 16-bit multipliers ideal for fast, real time digital signal processing applications. The X and Y operands along with their mode controls (TCX and TCY) have 17-bit input registers. The mode controls independently specify the operands as either two's complement or unsigned magnitude format, thereby.
HSP45106 : DSP Block. 16-Bit Numerically Controlled Oscillator. The Intersil is a high performance 16-bit quadrature Numerically Controlled Oscillator (NCO16). The NCO16 simplifies applications requiring frequency and phase agility such as frequency-hopped modems, PSK modems, spread spectrum communications, and precision signal generators. As shown in the block diagram, the HSP45106 is divided into a Phase/ Frequency.
SM320C6201B : TMS320 Family. Digital Signal Processor. Signal Processor (DSP) 5-, 6.7-ns Instruction Cycle Time 150 and 200-MHz Clock Rate Eight 32-Bit Instructions/Cycle 1200 and 1600 MIPS VelociTI Advanced Very Long Instruction Word (VLIW) C62x CPU Core Eight Independent Functional Units: Six ALUs (32-/40-Bit) Two 16-Bit Multipliers (32-Bit Results) Load-Store Architecture With 32 32-Bit.
SMJ320LC549 : Fixed Point DSPS. D Processed to MIL-PRF-38535 (QML) D Advanced Multibus Architecture With Three D Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators x 17-Bit Parallel Multiplier Coupled a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate.
TMS320BC53SPZ : TMS320 Family->TMS320C5X Fixed Point DSP. ti TMS320BC53S, Digital Signal Processor.
TMS320C44 : 320 Family. Digital Signal Processor. Highest Performance Floating-Point Digital Signal Processor (DSP) TMS320C44-60: 33-ns Instruction Cycle Time, 330 MOPS, 60 MFLOPS, 30 MIPS, 336M Bytes TMS320C44-50: 40-ns Instruction Cycle Time Four Communication Ports Six-Channel Direct Memory Address (DMA) Coprocessor Single-Cycle Conversion to and From IEEE-754 Floating-Point Format Single Cycle,.
TMS320C6202-200 : TMS320 Family. Signal Processors (DSPs) 4-, 3.33-ns Instruction Cycle Time 250-, 300-MHz Clock Rate Eight 32-Bit Instructions/Cycle MIPS C6202 and C6203B GLS Ball Grid Array (BGA) Packages are Pin-Compatible With the C6204 GLW BGA Package C6202B and C6203B GNZ and GNY Packages are Pin-Compatible VelociTI Advanced Very-Long-InstructionWord (VLIW) C62x DSP Core Eight.
TMS320C82 : 320 Family. Digital Signal Processor. Single Chip Parallel MIMD DSP Over 1.5 Billion RISC-like Operations per Second Master Processor (MP) - 32-Bit RISC Processor - IEEE-754 Floating Point - 4K-Byte Instruction Cache - 4K-Byte Data Cache Two Parallel Processors (PPs) - 32-Bit Advanced DSP Processors - 64-Bit Opcode Provides Many Parallel Operations per Cycle - 4K-Byte Instruction Cache,.
TMS320F2812 : TMS320 Family. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other s are subject to change without notice. IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products.
TMS320VC33PGE120 : TMS320 Family->TMS320C33 Floating Point DSP. ti TMS320VC33, Digital Signal Processor.
VP16256-27 : Digital Filtering. VP16256 - Programmable FIR Filter. The VP16256 contains sixteen multiplier - accumulators, which can be multi cycled to provide from to 128 stages of digital filtering. Input data and coefficients are both represented by 16-bit two's complement numbers with coefficients converted internally to 12 bits and the results being accumulated to 32 bits. In 16-tap mode the device samples data.
Z89223 : ROM (KB) = -- ;; RAM = -- ;; Speed = 20 ;; I/O = 20 ;; 8-bit Timers = 3 ;; Comm Interfaces = Spi ;; Other = PWM ;; Voltage = 4.5-5.5V ;;.
TMS320F2802 : 32-Bit Digital Signal Controller with Flash The TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802, and TMS320C2801 devices, members of the TMS320C28x™ DSP generation, are highly integrated, high-performance solutions for demanding control applications. UCD9501 is a member of the same device family specifically targeting power.
MC56F8036PB : The 56F8036 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs). It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program.