Details, datasheet, quote on part number: TMS320C64XDSP
PartTMS320C64XDSP
CategoryDSPs (Digital Signal Processors) => 320 Family
Title320 Family
DescriptionCpu, Memory And Peripheral System
CompanyTexas Instruments, Inc.
DatasheetDownload TMS320C64XDSP datasheet
  

 

Features, Applications

The world's highest performance DSP core, scalable to 1.1 GHz and beyond. New two-level cache supports the high-performance C64xTM DSP core. Enhanced Direct Memory Access (DMA) provides more than GB of sustained bandwidth. Synchronous External Memory Interfaces (EMIFs) and Host Interface provide over GB of bandwidth. Complete software compatibility with the programmable TMS320C6000TM DSP platform.

The World's Fastest DSPs Complemented by a HighPerformance Memory and Peripheral System

The TMS320C64xTM DSP core scales operating speeds beyond 1 GHz and achieves 10X performance improvements over the industry's previous DSP performance leader, the TMS320C62xTM DSP. Chips in development couple this processing performance with a new memory and peripheral system designed to accelerate realtime throughput for higher system performance. The C64xTM DSP core provides greater overall efficiency for demanding applications such as digital subscriber line

access multiplexers (DSLAMs), broadband video transcoding, streaming video servers, highspeed raster image processing (RIP) engines and network cameras. Full object code compatibility with existing C62xTM DSPs allows system developers to work on next-generation C64xTM DSP designs today. Highlights of the C64xTM DSP Core VelociTI.2TM architecture extensions with new instructions to accelerate performance in key applications Increased parallelism with dual 16-bit or quad 8-bit operations, and two x 16 bit multiplies or four x 8 bit multiplies

Packed data processing for formatting data within registers so that instructions can operate directly Initial devices are expected to operate - 800 MHz with scalable performance to over 1.1 GHz Improved orthogonality with frequently used instructions available in more functional units Double the bandwidth resulting from more registers, wider load/store data paths and enlarged 2-level cache Completely software compatible with C62x DSPs

TMS320C64xTM DSP Core Instruction Fetch Instruction Dispatch Instruction Decode Data Path 1 Register File A Control Registers Interrupt Control In-Circuit Emulation Data Path 2 Register File B

McBSP 0 McBSP 1 McBSP 2 Timer 0 Timer 1 Timer 2 Power Down Logic

The C64xTM DSP core couples its processing performance with a new memory and peripheral system designed to accelerate real-time throughput for higher system performance.

TMS320C64xTM DSP L1/L2 Cache A New Memory and Peripheral System That Measures Up The new C64xTM DSP memory and peripheral system includes a variety of features designed to help developers maximize the many performance advantages of the C64x DSP core:

The two-level cache has been scaled for initial implementation to support the high performance of the core, with 16 Kbytes each in Level 1 data and Level 1 program caches and 128 Kbytes in the unified Level 2 cache. For applications that require greater data determinism, the four associative sets or "ways" of the Level 2 cache can be redefined individually as blocks of memory with fixed addressing.

The C64xTM DSP L1/L2 cache sustains core performance at high clock rates.

A 32-channel DMA controller with a highly efficient transfer engine provides more than 2 GB/sec of sustained bandwidth, resulting in faster system performance. Thirty-two channels can be programmed to perform one or more of these tasks in the background of core program execution. Channels can be configured to run continuously throughout the device's entire operation, with only an initial configuration required. Each independently synchronized channel has a dedicated programmable parameter set. The user can configure address modification and stride independently for source and destination. Each channel can be configured to perform fixed, one-dimensional or two-dimensional transfers. Two-dimensional transfers allow automatic interleaving and de-interleaving of data streams and buffers, as well as the movement of sections of 2D

images. A total of 85 parameter sets are available and allow sophisticated linking of transfers. This flexibility permits auto-initializing circular buffers and the background movement of complex data structures.

A 64-bit synchronous External Memory Interface (EMIF), a 16-bit secondary EMIF for peripherals, and a 32-bit Host Port Interface provide over GB of bandwidth on initial implementations. The EMIFs can be clocked independently of the CPU, allowing them to support a wide variety of advanced synchronous and asynchronous external memory devices, including PC100 and PC 133 SDRAMs and various synchronous SRAM standards.

entire ST-Bus span of telephony channels. Direct connect to the ST-Bus allows an easy interface to a variety of H.110/100 and T1/E1 framing devices. The highly flexible and programmable framing, clocking, and baud rate of the McBSPs allow direct interface to multiple high performance audio codecs, including those supporting the AC97 and IIS standards.

Three multi-channel buffered serial ports (McBSPs) support a variety of audio and telecom standards. One hundred twenty-eight independently selectable time slots provide full connectivity to an

Scalable to 1.1 GHz The C64x DSP core uses advanced process technologies (0.15 micron for the initial devices, moving to 0.1 micron in the future) plus innovative logic circuit and design methodologies that focus on minimal wire lengths and low gate counts per clock. Compared to traditional approaches, there are only half the switching wires and transistors needed for the same amount of work. As a result, the C64x DSP core can achieve incredibly high performance to 1.1 GHz.

MHz MIPS 16-bit MMACs 8-bit MMACs Communications Imaging Code size reduction
Special purpose instructions Special purpose instructions Advanced instruction packing

support for loops on byte or half-word boundaries and the new SUBABS4 instruction. Morphology - The C64x DSP core provides more than 15X the performance for grayscale operations due to the presence of logical instructions in the.D unit, increased parallelism, and greater scheduling flexibility provided by additional registers.

Overall, the C64xTM DSP core, with advanced VelociTI.2TM VLIW architecture extensions, provides ten times the performance of the industry-leading C62xTM DSP core.

Unbeatable Performance The TMS320C6000TM DSP platform's 1st and 2nd generation comparison chart summarizes the performance advantages of the C64xTM DSP core with TI's advanced VelociTI.2TM architecture extensions.

Application Benchmarks Performance benchmarks a 750 MHz C64x DSP core against the industry leading 300 MHz C62xTM DSP core show that the C64x DSP core achieves far better performance than would be expected on the basis of clock rate alone. This is the result of hardware enhancements, plus the increased performance of the C6000TM DSP platform compiler. To view performance benchmarks visit: www.ti.com/sc/c6000benchmarks

increased parallelism for multiply accumulate operations. Reed Solomon Decode ­ The to 12X improvement here results in a large part from use of the new Galois Field Multiply instruction. Viterbi Decode (GSM) ­ This 7X improvement stems from the additional registers available for state variables and the new MAX and MIN instructions. FFT ­ The 5X improvement here results from the dual 16-bit architecture of the C64x DSP core, plus the new Bit Reverse instruction.

Benchmarks of typical routines used in communications applications show that the C64xTM DSP core to 12 times faster than the C62xTM DSP core.

Digital Communications The C64x DSP core achieves performance improvements to 12X the performance of the C62x DSP core on key routines: Filtering ­ The 5X improvement on 16-bit data is largely the result of

Imaging and Video For imaging and video applications, the C64x DSP core achieves improvements to 19X compared to the C62x DSP core on key routines: IDCT ­ This 5X improvement results from the dual 16-bit mathematical capabilities of the C64x DSP core. Motion Estimation ­ The 19X improvement here comes not only from quad 8-bit support, but also from non-aligned load

Benchmarks of typical routines used in imaging and video applications show that the C64xTM DSP core to 19 times faster than the C62xTM DSP core.


 

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