Details, datasheet, quote on part number: TMS320C6701-150
PartTMS320C6701-150
CategoryDSPs (Digital Signal Processors) => TMS320 Family
TitleTMS320 Family
Description
CompanyTexas Instruments, Inc.
DatasheetDownload TMS320C6701-150 datasheet
Quote
Find where to buy
 
  

 

Features, Applications

Signal Processor (DSP) 6.7-, 6-ns Instruction Cycle Time 150-, 167-MHz Clock Rate ­ Eight 32-Bit Instructions/Cycle ­ 1 GFLOPS ­ TMS320C6201 Fixed-Point DSP Pin-Compatible VelociTITM Advanced Very Long Instruction Word (VLIW) 'C67x CPU Core ­ Eight Highly Independent Functional Units: ­ Four ALUs (Floating- and Fixed-Point) ­ Two ALUs (Fixed-Point) ­ Two Multipliers (Floating- and Fixed-Point) ­ Load-Store Architecture With 32 32-Bit General-Purpose Registers ­ Instruction Packing Reduces Code Size ­ All Instructions Conditional Instruction Set Features ­ Hardware Support for IEEE Single-Precision Instructions ­ Hardware Support for IEEE Double-Precision Instructions ­ Byte-Addressable 16-, 32-Bit Data) ­ 8-Bit Overflow Protection ­ Saturation ­ Bit-Field Extract, Set, Clear ­ Bit-Counting ­ Normalization 1M-Bit On-Chip SRAM ­ 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) ­ 512K-Bit Dual-Access Internal Data (64K Bytes) 32-Bit External Memory Interface (EMIF) ­ Glueless Interface to Synchronous Memories: SDRAM and SBSRAM ­ Glueless Interface to Asynchronous Memories: SRAM and EPROM ­ 52M-Byte Addressable External Memory Space Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel

­ Access to Entire Memory Map Two Multichannel Buffered Serial Ports (McBSPs) ­ Direct Interface to T1/E1, MVIP, SCSA Framers ­ ST-Bus-Switching Compatible to 256 Channels Each AC97-Compatible ­ Serial-Peripheral-Interface (SPI) Compatible (MotorolaTM) Two 32-Bit General-Purpose Timers Flexible Phase-Locked-Loop (PLL) Clock Generator IEEE-1149.1 (JTAG) Boundary-Scan-Compatible 352-Pin Ball Grid Array (BGA) Package (GJC Suffix) 0.18-µm/5-Level Metal Process ­ CMOS Technology 3.3-V I/Os, 1.8-V Internal 150-MHz) 3.3-V I/Os, 1.9-V Internal (167-MHz Only)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VelociTI is a trademark of Texas Instruments. Motorola is a trademark of Motorola, Inc. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

description. 3 device characteristics. 3 functional block and CPU diagram. 4 CPU description. 5 signal groups description. 7 signal descriptions. 9 development support. 20 documentation support. 24 clock PLL. 25 absolute maximum ratings over operating case temperature range. 27 recommended operating conditions. 27 electrical characteristics over recommended ranges of supply voltage and operating case temperature. 28 parameter measurement information. 29 signal-transition levels. 29 input and output clocks. 30 asynchronous memory timing. 33 synchronous-burst memory timing. 35 synchronous DRAM timing. 39 HOLD/HOLDA timing. 43 reset timing. 44 external interrupt timing. 46 host-port interface timing. 47 multichannel buffered serial port timing. 50 DMAC, timer, power-down timing. 61 JTAG test-port timing. 63 mechanical data. 64

description

The TMS320C67x DSPs are the floating-point DSP family in the TMS320C6000TM DSP platform. The TMS320C6701 ('C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. With performance to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 167 MHz, the 'C6701 offers cost-effective solutions to high-performance DSP programming challenges. The 'C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The 'C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The 'C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The 'C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals. The 'C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a WindowsTM debugger interface for visibility into source code execution.

Table 1 provides an overview of the 'C6701 DSP. The table shows significant features of each device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count, etc. Table 1. Characteristics of the 'C6701 Processors

HARDWARE FEATURES EMIF DMA Peripherals Peri herals Host-Port Interface (HPI) McBSPs 32-Bit Timers Size (Bytes) Internal Program Memory Internal Data Memory Frequency Cycle Time Organization Size (Bytes) Organization MHz ns Core (V) I/O (V) PLL Options BGA Package Process Technology Product Status CLKIN frequency multiplier mm µm Product Preview (PP) Advance Information (AI) Production Data (PD) 2 64K Bytes Cache/Mapped Program 64K 2 Blocks: Eight 16-Bit Banks per Block 50/50 Split 8.3 ns Voltage 1.9 ('6701-167 only) 3.3 Bypass x4 352-pin GJC µm PD

is a trademark of Texas Instruments. Windows is a registered trademark of Microsoft Corporation.

 

Related products with the same datasheet
TMS320C6701-167
Some Part number from the same manufacture Texas Instruments, Inc.
TMS320C6701-167
TMS320C6701GJC Floating-point Digital Signal Processor
TMS320C6701GJC150 ti TMS320C6701, Floating-point Digital Signal Processor
TMS320C6711 Floating-point Digital Signal Processor
TMS320C6711-100
TMS320C6711B-100
TMS320C6711BGFN100 ti TMS320C6711B, Floating-point Digital Signal Processor
TMS320C6711CGDP200 ti TMS320C6711C, Floating-point Digital Signal Processor
TMS320C6711GFN Floating-point Digital Signal Processor
TMS320C6711GFN100 ti TMS320C6711, Floating-point Digital Signal Processor
TMS320C6712 Floating-point Digital Signal Processor
TMS320C6712-100
TMS320C6712C Floating-point Digital Signal Processors
TMS320C6712CGDP150 ti TMS320C6712C, Floating-point Digital Signal Processors
TMS320C6712GFN100 ti TMS320C6712, Floating-point Digital Signal Processor
TMS320C6713 Floating-point Digital Signal Processor.<<<>>>the TMS320C67x DSPS (including The TMS320C6713 And TMS320C6713B Devices) Compose The Floating-point DSP Generation in The TMS320C6000 DSP Platform. The C6713
TMS320C6713-150
TMS320C6713BGDP225 Floating-point Digital Signal Processor.<<<>>>the TMS320C67x DSPS (including The TMS320C6713 And TMS320C6713B Devices) Compose The Floating-point DSP Generation in The TMS320C6000 DSP Platform. The C6713
TMS320C6713GDP225 ti TMS320C6713, Floating-point Digital Signal Processor
TMS320C6713GDPA200 Floating-point Digital Signal Processor.<<<>>>the TMS320C67x DSPS (including The TMS320C6713 And TMS320C6713B Devices) Compose The Floating-point DSP Generation in The TMS320C6000 DSP Platform. The C6713
TMS320C6713GDPA200 ti TMS320C6713, Floating-point Digital Signal Processor
Same catergory

5962-9760601NXB : TMS320 Family->TMS320C3X Floating Point DSP. ti SMQ320LC31, Military Digital Signal Processors.

BSP-15 : Broadband Signal Processor. Equator makes no warranty for the use of its products, assumes no responsibility for any errors which may appear in this document, and makes no commitment to update the information contained herein. Equator reserves the right to change or discontinue this product at any time, without notice. There are no express or implied licenses granted hereunder.

CS4210 : 320 Family. Geode Ieee 1394 Ohci Controller (preliminary). The National Semiconductor® GeodeTM is a PCIbased IEEE 1394 OHCI (Open Host Controller Interface) controller. The CS4210 provides an implementation of the IEEE 1394 Link Layer functionality according to the programming model defined by 1394 OHCI Version 1.0. It supports high speed serial communication to 400 Mbits per second. The is an implementation.

CS7410 : Audio DSPs. CD/MP3 & Compressed Audio Decoder.

DSP56001 : 56XXX Family. 24-bit General Purpose Digital Signal Processor. MOTOROLA SEMICONDUCTOR TECHNICAL DATA 24-Bit General Purpose Digital Signal Processor Ceramic Quad Flat Pack (CQFP) The is a member of Motorola's family of Available a 132 pin, small footprint, HCMOS, low-power, general purpose Digital Signal surface mount package. Processors. The DSP56001 512 words of full speed, on-chip program RAM (PRAM) memory,.

DSP56853 : 16-bit Digital Signal Processor. 120 MIPS x 16-bit Program SRAM x 16-bit Data SRAM Serial Port Interface (SPI) 8-bit Parallel Host Interface General Purpose 16-bit Quad Timer JTAG/Enhanced On-Chip Emulation (OnCETM) for unobtrusive, real-time debugging Computer Operating Properly (COP)/Watchdog Timer Time-of-Day (TOD) 128 LQFP package to 41 GPIO x 16-bit Boot ROM Access to 2M words.

DSP56F803BU80 : DSP56800. DSP56F803 16-bit Digital Signal Processor. to 40 MIPS at 80MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture Hardware DO and REP loops MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes × 16-bit words Program Flash × 16-bit words Program RAM × 16-bit words Data Flash × 16-bit words Data RAM × 16-bit.

SM320C50GFAM50 : TMS320 Family->TMS320C5X Fixed Point DSP. ti SM320C50, Digital Signal Processors.

T8302 : DSP Block. Internet Protocol Telephone Advanced Rick Machine (ARM).. T8302 Internet Protocol Telephone Advanced RISC Machine (ARM Ethernet QoS Using IEEE ® 802.1q The Agere Systems, Inc. Voice over Internet Protocol (VoIP) Phone-On-A-ChipTM solution currently implements a quality of service (QoS) strategy that uses a proprietary voice packet prioritization scheme called Ethernet Quality of Service using BlackBurst (EQuB).

TMP320C50KGD : 320 Family. Digital Signal Processor Known Good Die. Instruction Execution Time for 5-V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3-V Operation Source-Code Compatible With All 'C1x and 'C2x Devices RAM-Based Operation × 16-Bit Single-Access On-Chip Program/ Data RAM × 16-Bit Dual-Access On-Chip Data RAM × 16-Bit On-Chip Boot ROM × 16-Bit Maximum Addressable External Memory Space (64K-Word.

TMS320C30GEL : TMS320 Family->TMS320C3X Floating Point DSP. ti TMS320C30, Digital Signal Processor.

TMS320C6416-400 : TMS320 Family. Signal Processors (DSPs) 1.67-, 1.39-ns Instruction Cycle Time 600-, 720-MHz Clock Rate ­ Eight 32-Bit Instructions/Cycle ­ Twenty-Eight Operations/Cycle MIPS ­ Fully Software-Compatible With ­ C6414/15/16 Devices Pin-Compatible VelociTI.2 Extensions to VelociTI Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x DSP Core ­ Eight Highly Independent.

TMS320LC31PQ40 : TMS320 Family->TMS320C3X Floating Point DSP. ti TMS320LC31, Digital Signal Processor.

TMS320VC33-120 : TMS320 Family. Signal Processor (DSP): ­ 13-ns Instruction Cycle Time ­ 150 Million Floating-Point Operations Per Second (MFLOPS) ­ 75 Million Instructions Per Second (MIPS) ­ 17-ns Instruction Cycle Time ­ 120 MFLOPS ­ 60 MIPS 32-Bit (1.1-Mbit) On-Chip Words of Dual-Access Static Random-Access Memory (SRAM) Configured × 16K Plus × 1K Blocks to Improve Internal Performance.

TMS320VC5402-100 : TMS320 Family. Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators × 17-Bit Parallel Multiplier Coupled a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation Compare, Select, and Store Unit (CSSU) for the Add/Compare.

 
0-C     D-L     M-R     S-Z