Details, datasheet, quote on part number: TMS320C6701-150
CategoryDSPs (Digital Signal Processors) => TMS320 Family
TitleTMS320 Family
CompanyTexas Instruments, Inc.
DatasheetDownload TMS320C6701-150 datasheet
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Features, Applications

Signal Processor (DSP) 6.7-, 6-ns Instruction Cycle Time 150-, 167-MHz Clock Rate ­ Eight 32-Bit Instructions/Cycle ­ 1 GFLOPS ­ TMS320C6201 Fixed-Point DSP Pin-Compatible VelociTITM Advanced Very Long Instruction Word (VLIW) 'C67x CPU Core ­ Eight Highly Independent Functional Units: ­ Four ALUs (Floating- and Fixed-Point) ­ Two ALUs (Fixed-Point) ­ Two Multipliers (Floating- and Fixed-Point) ­ Load-Store Architecture With 32 32-Bit General-Purpose Registers ­ Instruction Packing Reduces Code Size ­ All Instructions Conditional Instruction Set Features ­ Hardware Support for IEEE Single-Precision Instructions ­ Hardware Support for IEEE Double-Precision Instructions ­ Byte-Addressable 16-, 32-Bit Data) ­ 8-Bit Overflow Protection ­ Saturation ­ Bit-Field Extract, Set, Clear ­ Bit-Counting ­ Normalization 1M-Bit On-Chip SRAM ­ 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) ­ 512K-Bit Dual-Access Internal Data (64K Bytes) 32-Bit External Memory Interface (EMIF) ­ Glueless Interface to Synchronous Memories: SDRAM and SBSRAM ­ Glueless Interface to Asynchronous Memories: SRAM and EPROM ­ 52M-Byte Addressable External Memory Space Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel

­ Access to Entire Memory Map Two Multichannel Buffered Serial Ports (McBSPs) ­ Direct Interface to T1/E1, MVIP, SCSA Framers ­ ST-Bus-Switching Compatible to 256 Channels Each AC97-Compatible ­ Serial-Peripheral-Interface (SPI) Compatible (MotorolaTM) Two 32-Bit General-Purpose Timers Flexible Phase-Locked-Loop (PLL) Clock Generator IEEE-1149.1 (JTAG) Boundary-Scan-Compatible 352-Pin Ball Grid Array (BGA) Package (GJC Suffix) 0.18-µm/5-Level Metal Process ­ CMOS Technology 3.3-V I/Os, 1.8-V Internal 150-MHz) 3.3-V I/Os, 1.9-V Internal (167-MHz Only)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VelociTI is a trademark of Texas Instruments. Motorola is a trademark of Motorola, Inc. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

description. 3 device characteristics. 3 functional block and CPU diagram. 4 CPU description. 5 signal groups description. 7 signal descriptions. 9 development support. 20 documentation support. 24 clock PLL. 25 absolute maximum ratings over operating case temperature range. 27 recommended operating conditions. 27 electrical characteristics over recommended ranges of supply voltage and operating case temperature. 28 parameter measurement information. 29 signal-transition levels. 29 input and output clocks. 30 asynchronous memory timing. 33 synchronous-burst memory timing. 35 synchronous DRAM timing. 39 HOLD/HOLDA timing. 43 reset timing. 44 external interrupt timing. 46 host-port interface timing. 47 multichannel buffered serial port timing. 50 DMAC, timer, power-down timing. 61 JTAG test-port timing. 63 mechanical data. 64


The TMS320C67x DSPs are the floating-point DSP family in the TMS320C6000TM DSP platform. The TMS320C6701 ('C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. With performance to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 167 MHz, the 'C6701 offers cost-effective solutions to high-performance DSP programming challenges. The 'C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The 'C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The 'C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The 'C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals. The 'C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a WindowsTM debugger interface for visibility into source code execution.

Table 1 provides an overview of the 'C6701 DSP. The table shows significant features of each device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count, etc. Table 1. Characteristics of the 'C6701 Processors

HARDWARE FEATURES EMIF DMA Peripherals Peri herals Host-Port Interface (HPI) McBSPs 32-Bit Timers Size (Bytes) Internal Program Memory Internal Data Memory Frequency Cycle Time Organization Size (Bytes) Organization MHz ns Core (V) I/O (V) PLL Options BGA Package Process Technology Product Status CLKIN frequency multiplier mm µm Product Preview (PP) Advance Information (AI) Production Data (PD) 2 64K Bytes Cache/Mapped Program 64K 2 Blocks: Eight 16-Bit Banks per Block 50/50 Split 8.3 ns Voltage 1.9 ('6701-167 only) 3.3 Bypass x4 352-pin GJC µm PD

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