Details, datasheet, quote on part number: TMS320C6701GJCA120
PartTMS320C6701GJCA120
CategorySemiconductors => Processors => Digital Signal Processors => C6000 DSP => Other C6000 DSP
Part familyTMS320C6701 Floating-Point Digital Signal Processor
TitleTMS320 Family
DescriptionFloating-Point Digital Signal Processor 352-FCBGA
CompanyTexas Instruments, Inc.
StatusACTIVE
ROHSTBD
SampleNo
DatasheetDownload TMS320C6701GJCA120 datasheet
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Specifications 
RatingCatalog
DSP1 C67x
Approx. Price (US$)87.00 | 1ku
  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
352GJCFCBGAS-PBGA-N24JEDEC TRAY (5+1)A120 353531.27
Application notes
• TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A)
Interfacing external asynchronous static RAM (ASRAM) to the Texas Instruments (TI™) TMS320C6000 series of digital signal processors (DSPs) is simple compared to previous generations of TI DSPs, thanks to the advanced external memory interface (EMIF). The | Doc
• TMS320C6000 EMIF to External Flash Memory (Rev. A)
Interfacing external flash memory to the Texas Instruments TMS320C6000™ digital signal processor (DSP) is simple compared to previous generations of TI DSPs. The TMS320C6000 advanced external memory interface (EMIF) provides a glueless interface to a var | Doc
• TMS320C6000 C Compiler: C Implementation of Intrinsics
The first optimization step that you can perform on C source code for the TMS320C62xx is to use intrinsic operators. Intrinsics are used like functions and produce assembly language statements that would otherwise be inexpressible in C. The problem is that | Doc
• Using IBIS Models for Timing Analysis (Rev. A)
Today?s high-speed interfaces require strict timings and accurate system design. To achieve the necessary timings for a given system, input/output buffer information specification (IBIS) models must be used. These models accurately represent the device dri | Doc
• TMS320C6000 McBSP: IOM-2 Interface (Rev. A)
This document describes how the multi-channel buffered serial port (McBSP) in the Texas Instruments (TI) TMS320C6000? (C6000?) digital signal processor (DSP) family is used to communicate to an ISDN Oriented Modular Interface Revision 2 (IOM-2) bus-complia | Doc
• TMS320C6000 Board Design: Considerations for Debug (Rev. C) | Doc
• TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A)
This application report describes the interface between the Texas Instruments (TI) TMS320C6000™ digital signal processor (DSP) host port and the Intel 80960 microprocessor. The document includes schematics showing connections between the two devices, PAL | Doc
• TMS320C6000 DMA Example Applications (Rev. A)
The TMS320C6000? on-chip direct memory access (DMA) controller from Texas Instruments is used to transfer data between two locations in the memory map in the background of CPU operation. Typically, the DMA is used to:Transfer blocks of data between externa | Doc
• TMS320C6000 McBSP: Interface to SPI ROM (Rev. C)
The TMS320C6000? (C6000?) Multichannel Buffered Serial Port (McBSP) is designed to interface to a device that supports synchronous Serial Peripheral Interface (SPI). This document describes the hardware interface between the McBSP and a SPI ROM. The McBSP | Doc
• TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E)
Interfacing external SDRAM to the Texas Instruments TMS320C6000™ digital signal processor (DSP) is simple, compared to previous generations of TI DSPs, because of the advanced external memory interface (EMIF). The EMIF is a glueless interface to a variet | Doc
• TMS320C620x/TMS3206701 DMA and CPU: Data Access Performance (Rev. A)
In a real-time system, data flow is important to understand and control to achieve high performance. By analyzing the timing characteristics for accessing data and switching between data requestors, it is possible to maximize the achievable bandwidth in an | Doc
• TMS320C6000 Memory Test (Rev. A)
This set of programs has been compiled to provide a way to verify the integrity of internal DSP memory and external system memory for all devices currently in the TMS320C6000™ (C6000) family. Included with the memory test are all source files, the Code C | Doc
• TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D)
Texas Instruments TMS320C6000™ digital signal processors (DSPs) provide a variety of boot configurations that determine which actions are performed after device reset, to prepare for initialization. The boot process is determined by latching the boot con | Doc
• TMS320C6000 Host Port to MPC860 Interface (Rev. A)
This application report describes an interface between the Motorola MPC860 microprocessor and the host port interface (HPI) of a Texas Instruments TMS320C6000™ (C6000™) digital signal processor (DSP) device. This document includes a schematic showing c | Doc
• Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A)
This document describes how to use the mulit-channel buffered serial ports (McBSP) in the Texas Instruments (TI) TMS320C6000™ digital signal processor (DSP) as a high-speed data communication port.One McBSP of one C6000™ DSP device can be connected to | Doc
• TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A)
This document describes how to interface the multichannel buffered serial port (McBSP) in the TMS320C6000? digital signal processor (DSP) to a voice band audio processor (VBAP). The VBAP under discussion is the TI TLV320AC56, 3V, 2.048 MHz audio processo | Doc
• TMS320C6000 McBSP: I2S Interface
This document describes how to use the multichannel buffered serial port (McBSP) in the Texas Instruments (TI)(TM) TMS320C6000 digital signal processors (DSP) to interface with devices that conform to the Inter-IC Sound (I2S) specification. I2S is a proto | Doc
• TMS320C6000 u-Law and a-Law Companding with Software or the McBSP
This document describes how to perform data companding with the TMS320C6000(tm)digital signal processors(DSP). Companding refers to the compression and expansion of transfer data before and after transmission, respectively.The multichannel buffered serial | Doc
• TMS320C62x/C67x Power Consumption Summary (Rev. C)
This document discusses the power consumption of the Texas Instruments TMS320C6201B, TMS320C6701, TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204, TMS320C6205, TMS320C6211, and TMS320C6711 digital signal processors (DSPs) for typical applications. The | Doc
• TMS320C6000 McBSP as a TDM Highway (Rev. A)
This document describes how the multichannel buffered serial ports (McBSP) in the TMS320C6000™ digital signal processors (DSP) are used to communicate on a time-division multiplexed (TDM) data highway.TDM provides multiple devices a time slot to perform | Doc
• TMS320C6201/6701 EVM: TMS320C6000 McBSP to Multimedia Audio Codec (Rev. A)
This application note describes how a multimedia audio codec can be interfaced to the TMS320C6201/C6701 DSPs. Although this application report uses the CS4231A audio codec as an example, a part that is obsolete, this application note can be used as a refer | Doc
• TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B)
This document describes how the multichannel buffered serial ports (McBSPs) in the Texas Instruments TMS320C6000™ digital signal processor (DSP) are used to communicate to a single-rate Serial Telecom (ST)-BUS-compliant device.The McBSP receives the fram | Doc
• TMS320C6000 System Clock Circuit Example (Rev. A)
This document describes how to provide the Texas Instruments TMS320C6000™ DSP with a system clock. All of the clocks internal to the C6000™ are generated from a single source through the CLKIN pin. This source clock for the device is an external signal | Doc
• Introduction to TMS320C6000 DSP Optimization
The TMS320C6000™ Digital Signal Processors (DSPs) have many architectural advantages that make them ideal for computation-intensive real-time applications. However, to fully leverage the architectural features that C6000™ processors offer, code optimiz | Doc
• Thermal Considerations for the DM64xx, DM64x, and C6000 Devices
As integrated circuit (IC) components become more complex, the challenge of producing an end product with superior thermal performance increases. Thermal performance is a system level concern, impacted by IC packaging as well as by printed circuit board (P | Doc
• TMS320C6000 Board Design for JTAG (Rev. C)
Designing a TMS320C6000™ DSP board to utilize all of the functionality of the JTAG scan path is a simple process, but a few considerations must be taken into account. The default state of the emulation signals determines whether the JTAG port is used for | Doc
• TMS320C6000 McBSP Initialization (Rev. C)
The TMS320C6000? multichannel buffered serial port (McBSP) can operate in a variety of modes, as per application requirements. For proper operation, the serial port must be initialized in a specific order. This document describes the initialization steps n | Doc
• Using a TMS320C6000 McBSP for Data Packing (Rev. A)
This application report describes how to use the multichannel buffered serial port (McBSP) in the Texas Instruments TMS320C6000™ digital signal processor (DSP) for data packing. Data packing involves moving either multiple successive 8-bit elements to/f | Doc
• TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C)
This application report describes an interface between the Texas Instruments TMS320C6000™ DSP host port and the PLX Technology PCI9050 (PCI9052), the PCI interface chip. The PCI9052 is functionally the same as the PCI9050. The only difference between the | Doc
• Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A)
This application report describes the architecture and capabilities of the AMCC S5933 PCI controller and how it can be interfaced to the TMS320C6201 digital signal processor (DSP). The DSP's host port interface (HPI) can be a PCI target, and its external m | Doc
• TMS320C6000 Host Port to MC68360 Interface (Rev. A)
This application report describes an interface between the Motorola MC68360 quad integrated communication controller (QUICC) and the host port interface (HPI) of a TMS320C6000™ (C6000™) digital signal processor (DSP) device. This includes a schematic s | Doc
• Circular Buffering on TMS320C6000 (Rev. A)
This application report explains how circular buffering is implemented on the TMS320C6000? devices. Circular buffering helps to implement finite impulse response (FIR) filters efficiently. Filters require delay lines or buffers of past (and current) sample | Doc
• How to Begin Development Today w/ High Performance Floating Point TMS320C67x DSP
This application report describes how you can begin development now for the Texas Instruments (TI™) TMS320C67x generation of high-performance digital signal processors (DSPs). Because of the compatibility between TMS320C6000 generation devices, existing C | Doc
• TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A)
This document describes how to use the multichannel buffered serial ports (McBSPs) in the Texas Instruments TMS320C6000™ digital signal processor (DSP) as a digital controller for an audio codec 1997 device.The McBSP is connected to a stereo audio codec | Doc
Evaluation Kits
TMDSEMU560V2STM-U: XDS560v2 System Trace USB Debug Probe
TMDSDSK6713: TMS320C6713 DSP Starter Kit (DSK)
TMDSEMU560V2STM-UE: XDS560v2 System Trace USB & Ethernet Debug Probe

 

Features, Applications

Signal Processor (DSP) 6.7-, 6-ns Instruction Cycle Time 150-, 167-MHz Clock Rate Eight 32-Bit Instructions/Cycle 1 GFLOPS TMS320C6201 Fixed-Point DSP Pin-Compatible VelociTITM Advanced Very Long Instruction Word (VLIW) 'C67x CPU Core Eight Highly Independent Functional Units: Four ALUs (Floating- and Fixed-Point) Two ALUs (Fixed-Point) Two Multipliers (Floating- and Fixed-Point) Load-Store Architecture With 32 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size All Instructions Conditional Instruction Set Features Hardware Support for IEEE Single-Precision Instructions Hardware Support for IEEE Double-Precision Instructions Byte-Addressable 16-, 32-Bit Data) 8-Bit Overflow Protection Saturation Bit-Field Extract, Set, Clear Bit-Counting Normalization 1M-Bit On-Chip SRAM 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) 512K-Bit Dual-Access Internal Data (64K Bytes) 32-Bit External Memory Interface (EMIF) Glueless Interface to Synchronous Memories: SDRAM and SBSRAM Glueless Interface to Asynchronous Memories: SRAM and EPROM 52M-Byte Addressable External Memory Space Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel

Access to Entire Memory Map Two Multichannel Buffered Serial Ports (McBSPs) Direct Interface to T1/E1, MVIP, SCSA Framers ST-Bus-Switching Compatible to 256 Channels Each AC97-Compatible Serial-Peripheral-Interface (SPI) Compatible (MotorolaTM) Two 32-Bit General-Purpose Timers Flexible Phase-Locked-Loop (PLL) Clock Generator IEEE-1149.1 (JTAG) Boundary-Scan-Compatible 352-Pin Ball Grid Array (BGA) Package (GJC Suffix) 0.18-m/5-Level Metal Process CMOS Technology 3.3-V I/Os, 1.8-V Internal 150-MHz) 3.3-V I/Os, 1.9-V Internal (167-MHz Only)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VelociTI is a trademark of Texas Instruments. Motorola is a trademark of Motorola, Inc. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

description. 3 device characteristics. 3 functional block and CPU diagram. 4 CPU description. 5 signal groups description. 7 signal descriptions. 9 development support. 20 documentation support. 24 clock PLL. 25 absolute maximum ratings over operating case temperature range. 27 recommended operating conditions. 27 electrical characteristics over recommended ranges of supply voltage and operating case temperature. 28 parameter measurement information. 29 signal-transition levels. 29 input and output clocks. 30 asynchronous memory timing. 33 synchronous-burst memory timing. 35 synchronous DRAM timing. 39 HOLD/HOLDA timing. 43 reset timing. 44 external interrupt timing. 46 host-port interface timing. 47 multichannel buffered serial port timing. 50 DMAC, timer, power-down timing. 61 JTAG test-port timing. 63 mechanical data. 64

description

The TMS320C67x DSPs are the floating-point DSP family in the TMS320C6000TM DSP platform. The TMS320C6701 ('C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. With performance to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 167 MHz, the 'C6701 offers cost-effective solutions to high-performance DSP programming challenges. The 'C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The 'C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The 'C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The 'C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals. The 'C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a WindowsTM debugger interface for visibility into source code execution.

Table 1 provides an overview of the 'C6701 DSP. The table shows significant features of each device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count, etc. Table 1. Characteristics of the 'C6701 Processors

HARDWARE FEATURES EMIF DMA Peripherals Peri herals Host-Port Interface (HPI) McBSPs 32-Bit Timers Size (Bytes) Internal Program Memory Internal Data Memory Frequency Cycle Time Organization Size (Bytes) Organization MHz ns Core (V) I/O (V) PLL Options BGA Package Process Technology Product Status CLKIN frequency multiplier mm m Product Preview (PP) Advance Information (AI) Production Data (PD) 2 64K Bytes Cache/Mapped Program 64K 2 Blocks: Eight 16-Bit Banks per Block 50/50 Split 8.3 ns Voltage 1.9 ('6701-167 only) 3.3 Bypass x4 352-pin GJC m PD

is a trademark of Texas Instruments. Windows is a registered trademark of Microsoft Corporation.

 

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