|Category||DSPs (Digital Signal Processors) => TMS320 Family|
|Company||Texas Instruments, Inc.|
|Datasheet||Download TMS320C6711-100 datasheet
Processors (DSPs): (TMS320C6711, C6711B, and C6711C) Eight 32-Bit Instructions/Cycle 200-MHz Clock Rates 5-ns Instruction Cycle Time MFLOPS VelociTI Advanced Very Long Instruction Word (VLIW) C67x DSP Core Eight Highly Independent Functional Units: Four ALUs (Floating- and Fixed-Point) Two ALUs (Fixed-Point) Two Multipliers (Floating- and Fixed-Point) Load-Store Architecture With 32 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size All Instructions Conditional Instruction Set Features Hardware Support for IEEE Single-Precision and Double-Precision Instructions Byte-Addressable 16-, 32-Bit Data) 8-Bit Overflow Protection Saturation Bit-Field Extract, Set, Clear Bit-Counting Normalization L1/L2 Memory Architecture (4K-Byte) L1P Program Cache (Direct Mapped) (4K-Byte) L1D Data Cache (2-Way Set-Associative) (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation) Device Configuration Boot Mode: HPI, 8-, 16-, and 32-Bit ROM Boot Endianness: Little Endian, Big Endian Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
Glueless Interface to Asynchronous Memories: SRAM and EPROM Glueless Interface to Synchronous Memories: SDRAM and SBSRAM 256M-Byte Total Addressable External Memory Space 16-Bit Host-Port Interface (HPI) Two Multichannel Buffered Serial Ports (McBSPs) Direct Interface to T1/E1, MVIP, SCSA Framers ST-Bus-Switching Compatible to 256 Channels Each AC97-Compatible Serial-Peripheral-Interface (SPI) Compatible (Motorola) Two 32-Bit General-Purpose Timers Flexible Phase-Locked-Loop (PLL) Clock Generator [C6711/11B] Flexible Software Configurable PLL-Based Clock Generator Module [C6711C] A Dedicated General-Purpose Input/Output (GPIO) Module With 5 Pins [C6711C] IEEE-1149.1 (JTAG) Boundary-Scan-Compatible 256-Pin Ball Grid Array (BGA) Package (GFN Suffix) [C6711/C6711B Only] 272-Pin Ball Grid Array (BGA) Package (GDP Suffix) [C6711C Only] CMOS Technology 0.13-µm/6-Level Copper Metal Process 0.18-µm/5-Level Copper Metal Process (C6711/11B) 3.3-V I/O, 1.26-V Internal (C6711C) 3.3-V I/O, 1.8-V Internal (C6711B/C6711100) 3.3-V I/O, 1.9-V Internal (C6711-150)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320C67x, VelociTI, and C67x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. All trademarks are the property of their respective owners. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
GFN BGA package (bottom view) [C6711/11B only]. 3 GDP BGA package (bottom view) [C6711C only]. 3 description. 4 device characteristics. 5 device compatibility. 6 functional block and CPU (DSP core) diagram. 7 CPU (DSP core) description. 8 memory map summary. 10 peripheral register descriptions. 11 signal groups description. 16 device configurations. 19 terminal functions. 22 development support. 33 documentation support. 36 CPU CSR register description. 37 interrupt sources and interrupt selector [C6711/11B only]. 39 interrupt sources and interrupt selector [C6711C only]. 40 EDMA channel synchronization events [C6711/11B only]. 41 EDMA module and EDMA selector [C6711C only]. 42 clock PLL [C6711/11B only]. 44 PLL and PLL controller [C6711C only]. 46 power-supply sequencing. 53 power-supply decoupling. 54 IEEE 1149.1 JTAG compatibility statement. 54 EMIF device speed. 55 bootmode. 56 absolute maximum ratings over operating case temperature range. 57 recommended operating conditions. 57 electrical characteristics over recommended ranges of supply voltage and operating case temperature for C6711/C6711B only. 58 electrical characteristics over recommended ranges of supply voltage and operating case temperature for C6711C only. 59 parameter measurement information. 60 signal transition levels. 61 timing parameters and board routing analysis. 61 input and output clocks. 63 asynchronous memory timing. 67 synchronous-burst memory timing. 71 synchronous DRAM timing. 75 HOLD/HOLDA timing. 82 BUSREQ timing. 83 reset timing [C6711/11B]. 84 reset timing [C6711C]. 86 external interrupt timing. 88 host-port interface timing. 89 multichannel buffered serial port timing. 95 timer timing. 114 general-purpose input/output (GPIO) port timing [C6711C only]. 115 JTAG test-port timing. 116 mechanical data [C6711/11B only]. 117 mechanical data [C6711C only]. 118 revision history. 119GFN 256-PIN BALL GRID ARRAY (BGA) PACKAGE (BOTTOM VIEW)
GDP 272-PIN BALL GRID ARRAY (BGA) PACKAGE (BOTTOM VIEW)
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