Details, datasheet, quote on part number: TMS320C6712CGDP150
PartTMS320C6712CGDP150
CategoryDSPs (Digital Signal Processors) => TMS320 Family
TitleTMS320 Family
Descriptionti TMS320C6712C, Floating-point Digital Signal Processors
CompanyTexas Instruments, Inc.
DatasheetDownload TMS320C6712CGDP150 datasheet
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Features, Applications

Processors (DSPs): TMS320C6712C) - Eight 32-Bit Instructions/Cycle 100-, 150-MHz Clock Rates 10-, 6.7-ns Instruction Cycle Times 600, 900 MFLOPS VelociTI Advanced Very Long Instruction Word (VLIW) C67x DSP Core - Eight Highly Independent Functional Units: - Four ALUs (Floating- and Fixed-Point) - Two ALUs (Fixed-Point) - Two Multipliers (Floating- and Fixed-Point) - Load-Store Architecture With 32 32-Bit General-Purpose Registers - Instruction Packing Reduces Code Size - All Instructions Conditional Instruction Set Features - Hardware Support for IEEE Single-Precision and Double-Precision Instructions - Byte-Addressable 16-, 32-Bit Data) - 8-Bit Overflow Protection - Saturation - Bit-Field Extract, Set, Clear - Bit-Counting - Normalization L1/L2 Memory Architecture (4K-Byte) L1P Program Cache (Direct Mapped) (4K-Byte) L1D Data Cache (2-Way Set-Associative) (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation) Device Configuration - Boot Mode: 8- and 16-Bit ROM Boot - Endianness: Little Endian Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)

- Glueless Interface to Asynchronous Memories: SRAM and EPROM - Glueless Interface to Synchronous Memories: SDRAM and SBSRAM - 256M-Byte Total Addressable External Memory Space Two Multichannel Buffered Serial Ports (McBSPs) - Direct Interface to T1/E1, MVIP, SCSA Framers - ST-Bus-Switching Compatible to 256 Channels Each AC97-Compatible - Serial-Peripheral-Interface (SPI) Compatible (Motorola) Two 32-Bit General-Purpose Timers Flexible Phase-Locked-Loop (PLL) Clock Generator [C6712] Flexible Software-Configurable PLL-Based Clock Generator Module [C6712C] A Dedicated General-Purpose Input/Output (GPIO) Module With 5 Pins [C6712C] IEEE-1149.1 (JTAG) Boundary-Scan-Compatible 256-Pin Ball Grid Array (BGA) Package (GFN Suffix) [C6712 Only] 272-Pin Ball Grid Array (BGA) Package (GDP Suffix) [C6712C Only] CMOS Technology - 0.13-µm/6-Level Copper Metal Process - 0.18-µm/5-Level Metal Process (C6712) 3.3-V I/Os, 1.26-V Internal (C6712C) 3.3-V I/Os, 1.8-V Internal (C6712)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320C67x, VelociTI, and C67x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. Other trademarks are the property of their respective owners. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

GFN BGA package (bottom view) [C6712 only]. 3 GDP BGA package (bottom view) [C6712C only]. 3 description. 4 device characteristics. 5 device compatibility. 6 functional block and CPU (DSP core) diagram. 7 CPU (DSP core) description. 8 memory map summary. 10 peripheral register descriptions. 11 signal groups description. 16 device configurations. 18 terminal functions. 20 development support. 32 documentation support. 35 CPU CSR register description. 36 interrupt sources and interrupt selector [C6712 only]. 38 interrupt sources and interrupt selector [C6712C only]. 39 EDMA channel synchronization events [C6712 only]. 40 EDMA module and EDMA selector [C6712C only]. 41 clock PLL [C6712 only]. 43 PLL and PLL controller [C6712C only]. 45 general-purpose input/output (GPIO). 52 power-supply sequencing. 53 power-supply decoupling. 54 IEEE 1149.1 JTAG compatibility statement. 54 EMIF device speed. 55 bootmode. absolute maximum ratings over operating case temperature range. recommended operating conditions. electrical characteristics over recommended ranges of supply voltage and operating case temperature.

parameter measurement information. 59 signal transition levels. 60 timing parameters and board routing analysis. 60 input and output clocks. 62 asynchronous memory timing. 67 synchronous-burst memory timing. 70 synchronous DRAM timing. 72 HOLD/HOLDA timing. 78 BUSREQ timing. 79 reset timing [C6712]. 80 reset timing [C6712C]. 82 external interrupt timing. 84 multichannel buffered serial port timing. 85 timer timing. 99 general-purpose input/output (GPIO) port timing [C6712C only]. 100 JTAG test-port timing. 101 mechanical data [C6712 only]. 102 mechanical data [C6712C only]. 103 revision history. 104

GFN 256-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW )
GDP 272-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW

 

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