Details, datasheet, quote on part number: TMS320C6712CGDP150
PartTMS320C6712CGDP150
CategorySemiconductors => Processors => Digital Signal Processors => C6000 DSP => Other C6000 DSP
Part familyTMS320C6712 Floating-Point Digital Signal Processor
TitleTMS320 Family
DescriptionFloating-Point Digital Signal Processor 272-BGA
CompanyTexas Instruments, Inc.
StatusOBSOLETE
ROHSNot Compliant
SampleNo
DatasheetDownload TMS320C6712CGDP150 datasheet
Quote
Find where to buy
 
  
  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
272GDPBGAS-PBGA-N 27271.781.27
Application notes
• TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A)
Interfacing external asynchronous static RAM (ASRAM) to the Texas Instruments (TI™) TMS320C6000 series of digital signal processors (DSPs) is simple compared to previous generations of TI DSPs, thanks to the advanced external memory interface (EMIF). The | Doc
• TMS320C6000 EMIF to External Flash Memory (Rev. A)
Interfacing external flash memory to the Texas Instruments TMS320C6000™ digital signal processor (DSP) is simple compared to previous generations of TI DSPs. The TMS320C6000 advanced external memory interface (EMIF) provides a glueless interface to a var | Doc
• TMS320C621x/TMS320C671x EDMA Architecture
The enhanced DMA (EDMA) controller of the TMS320C621x™/TMS320C671x™ device is a highly efficient data transfer engine. To maximize bandwidth, minimize transfer interference, and fully utilize the resources of the EDMA, it is crucial to understand the a | Doc
• TMS320C6000 C Compiler: C Implementation of Intrinsics
The first optimization step that you can perform on C source code for the TMS320C62xx is to use intrinsic operators. Intrinsics are used like functions and produce assembly language statements that would otherwise be inexpressible in C. The problem is that | Doc
• Using IBIS Models for Timing Analysis (Rev. A)
Today?s high-speed interfaces require strict timings and accurate system design. To achieve the necessary timings for a given system, input/output buffer information specification (IBIS) models must be used. These models accurately represent the device dri | Doc
• TMS320C6000 McBSP: IOM-2 Interface (Rev. A)
This document describes how the multi-channel buffered serial port (McBSP) in the Texas Instruments (TI) TMS320C6000? (C6000?) digital signal processor (DSP) family is used to communicate to an ISDN Oriented Modular Interface Revision 2 (IOM-2) bus-complia | Doc
• TMS320C6000 Board Design: Considerations for Debug (Rev. C) | Doc
• TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A)
This application report describes the interface between the Texas Instruments (TI) TMS320C6000™ digital signal processor (DSP) host port and the Intel 80960 microprocessor. The document includes schematics showing connections between the two devices, PAL | Doc
• TMS320C6000 DMA Example Applications (Rev. A)
The TMS320C6000? on-chip direct memory access (DMA) controller from Texas Instruments is used to transfer data between two locations in the memory map in the background of CPU operation. Typically, the DMA is used to:Transfer blocks of data between externa | Doc
• TMS320C6000 McBSP: Interface to SPI ROM (Rev. C)
The TMS320C6000? (C6000?) Multichannel Buffered Serial Port (McBSP) is designed to interface to a device that supports synchronous Serial Peripheral Interface (SPI). This document describes the hardware interface between the McBSP and a SPI ROM. The McBSP | Doc
• TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E)
Interfacing external SDRAM to the Texas Instruments TMS320C6000™ digital signal processor (DSP) is simple, compared to previous generations of TI DSPs, because of the advanced external memory interface (EMIF). The EMIF is a glueless interface to a variet | Doc
• TMS320C6000 Enhanced DMA: Example Applications (Rev. A)
The enhanced direct memory access (EDMA) controller is the backbone of the two-level cache architecture for the TMS320C6000? DSPs. The EDMA performs:o cache servicingo host-port servicingo user-programmable data transfers Through proper configuration, EDMA | Doc
• TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D)
Texas Instruments TMS320C6000™ digital signal processors (DSPs) provide a variety of boot configurations that determine which actions are performed after device reset, to prepare for initialization. The boot process is determined by latching the boot con | Doc
• TMS320C6000 Host Port to MPC860 Interface (Rev. A)
This application report describes an interface between the Motorola MPC860 microprocessor and the host port interface (HPI) of a Texas Instruments TMS320C6000™ (C6000™) digital signal processor (DSP) device. This document includes a schematic showing c | Doc
• TMS320C621x/671x EDMA Performance Data
The enhanced DMA (EDMA) controller of the TMS320C621x™/TMS320C671x™ devices is a highly efficient data transfer engine, capable of maintaining transfers at up to 1800 MB/sec at a 225 MHz CPU clock frequency. This document details actual bandwidth achie | Doc
• Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A)
This document describes how to use the mulit-channel buffered serial ports (McBSP) in the Texas Instruments (TI) TMS320C6000™ digital signal processor (DSP) as a high-speed data communication port.One McBSP of one C6000™ DSP device can be connected to | Doc
• TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A)
This document describes how to interface the multichannel buffered serial port (McBSP) in the TMS320C6000? digital signal processor (DSP) to a voice band audio processor (VBAP). The VBAP under discussion is the TI TLV320AC56, 3V, 2.048 MHz audio processo | Doc
• TMS320C6000 McBSP: I2S Interface
This document describes how to use the multichannel buffered serial port (McBSP) in the Texas Instruments (TI)(TM) TMS320C6000 digital signal processors (DSP) to interface with devices that conform to the Inter-IC Sound (I2S) specification. I2S is a proto | Doc
• TMS320C6000 u-Law and a-Law Companding with Software or the McBSP
This document describes how to perform data companding with the TMS320C6000(tm)digital signal processors(DSP). Companding refers to the compression and expansion of transfer data before and after transmission, respectively.The multichannel buffered serial | Doc
• TMS320C6000 McBSP as a TDM Highway (Rev. A)
This document describes how the multichannel buffered serial ports (McBSP) in the TMS320C6000™ digital signal processors (DSP) are used to communicate on a time-division multiplexed (TDM) data highway.TDM provides multiple devices a time slot to perform | Doc
• TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B)
This document describes how the multichannel buffered serial ports (McBSPs) in the Texas Instruments TMS320C6000™ digital signal processor (DSP) are used to communicate to a single-rate Serial Telecom (ST)-BUS-compliant device.The McBSP receives the fram | Doc
• TMS320C6000 System Clock Circuit Example (Rev. A)
This document describes how to provide the Texas Instruments TMS320C6000™ DSP with a system clock. All of the clocks internal to the C6000™ are generated from a single source through the CLKIN pin. This source clock for the device is an external signal | Doc
• TMS320C621x/C671x EDMA Queue Management Guidelines
The enhanced DMA (EDMA) controller of the TMS320C621x and TMS320C671x devices is a highly efficient data transfer engine, controlling all of the data movement beyond the level-two memory of the device. There are sixteen channels and a quick DMA (QDMA) avai | Doc
• TMS320C6000 Board Design for JTAG (Rev. C)
Designing a TMS320C6000™ DSP board to utilize all of the functionality of the JTAG scan path is a simple process, but a few considerations must be taken into account. The default state of the emulation signals determines whether the JTAG port is used for | Doc
• TMS320C6000 McBSP Initialization (Rev. C)
The TMS320C6000? multichannel buffered serial port (McBSP) can operate in a variety of modes, as per application requirements. For proper operation, the serial port must be initialized in a specific order. This document describes the initialization steps n | Doc
• TMS320C6711D, C6712D, C6713B Power Consumption Summary (Rev. A)
This document discusses the power consumption of the Texas Instruments TMS320C6711D, TMS320C6712D, and TMS320C6713B digital signal processors (DSPs). Power consumption on these devices is highly application dependent, so a spreadsheet is provided to model | Doc
• Using a TMS320C6000 McBSP for Data Packing (Rev. A)
This application report describes how to use the multichannel buffered serial port (McBSP) in the Texas Instruments TMS320C6000™ digital signal processor (DSP) for data packing. Data packing involves moving either multiple successive 8-bit elements to/f | Doc
• TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C)
This application report describes an interface between the Texas Instruments TMS320C6000™ DSP host port and the PLX Technology PCI9050 (PCI9052), the PCI interface chip. The PCI9052 is functionally the same as the PCI9050. The only difference between the | Doc
• Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A)
This application report describes the architecture and capabilities of the AMCC S5933 PCI controller and how it can be interfaced to the TMS320C6201 digital signal processor (DSP). The DSP's host port interface (HPI) can be a PCI target, and its external m | Doc
• How to Begin Development with the TMS320C6712 DSP
This application report describes how you can begin development now for the Texas Instruments TMS320C6712 digital signal processor (DSP) systems. The similarities and differences between the C6712 and the C6711 devices are briefly discussed. Because of the | Doc
• TMS320C6000 Host Port to MC68360 Interface (Rev. A)
This application report describes an interface between the Motorola MC68360 quad integrated communication controller (QUICC) and the host port interface (HPI) of a TMS320C6000™ (C6000™) digital signal processor (DSP) device. This includes a schematic s | Doc
• Circular Buffering on TMS320C6000 (Rev. A)
This application report explains how circular buffering is implemented on the TMS320C6000? devices. Circular buffering helps to implement finite impulse response (FIR) filters efficiently. Filters require delay lines or buffers of past (and current) sample | Doc
• How to Begin Development Today w/ High Performance Floating Point TMS320C67x DSP
This application report describes how you can begin development now for the Texas Instruments (TI™) TMS320C67x generation of high-performance digital signal processors (DSPs). Because of the compatibility between TMS320C6000 generation devices, existing C | Doc
• Migrating from TMS320C6712/C6712C to TMS320C6712D (Rev. F)
This document describes issues of interest related to migration from the Texas Instruments TMS320C6712 GFN package and TMS320C6712C GDP package to the TMS320C6712D digital signal processor (DSP) GDP package. The objective of this document is to indicate di | Doc
• TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A)
This document describes how to use the multichannel buffered serial ports (McBSPs) in the Texas Instruments TMS320C6000™ digital signal processor (DSP) as a digital controller for an audio codec 1997 device.The McBSP is connected to a stereo audio codec | Doc
• TMS320C6000 EDMA IO Scheduling and Performance
The enhanced DMA (EDMA) is a highly efficient and parallel data transfer engine. To make the best use of its resources, it is necessary to understand the architecture and schedule transfers intelligently. This document details how to summarize, analyze, an | Doc
Evaluation Kits
TMDSDSK6713: TMS320C6713 DSP Starter Kit (DSK)

 

Features, Applications

Processors (DSPs): TMS320C6712C) - Eight 32-Bit Instructions/Cycle 100-, 150-MHz Clock Rates 10-, 6.7-ns Instruction Cycle Times 600, 900 MFLOPS VelociTI Advanced Very Long Instruction Word (VLIW) C67x DSP Core - Eight Highly Independent Functional Units: - Four ALUs (Floating- and Fixed-Point) - Two ALUs (Fixed-Point) - Two Multipliers (Floating- and Fixed-Point) - Load-Store Architecture With 32 32-Bit General-Purpose Registers - Instruction Packing Reduces Code Size - All Instructions Conditional Instruction Set Features - Hardware Support for IEEE Single-Precision and Double-Precision Instructions - Byte-Addressable 16-, 32-Bit Data) - 8-Bit Overflow Protection - Saturation - Bit-Field Extract, Set, Clear - Bit-Counting - Normalization L1/L2 Memory Architecture (4K-Byte) L1P Program Cache (Direct Mapped) (4K-Byte) L1D Data Cache (2-Way Set-Associative) (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation) Device Configuration - Boot Mode: 8- and 16-Bit ROM Boot - Endianness: Little Endian Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)

- Glueless Interface to Asynchronous Memories: SRAM and EPROM - Glueless Interface to Synchronous Memories: SDRAM and SBSRAM - 256M-Byte Total Addressable External Memory Space Two Multichannel Buffered Serial Ports (McBSPs) - Direct Interface to T1/E1, MVIP, SCSA Framers - ST-Bus-Switching Compatible to 256 Channels Each AC97-Compatible - Serial-Peripheral-Interface (SPI) Compatible (Motorola) Two 32-Bit General-Purpose Timers Flexible Phase-Locked-Loop (PLL) Clock Generator [C6712] Flexible Software-Configurable PLL-Based Clock Generator Module [C6712C] A Dedicated General-Purpose Input/Output (GPIO) Module With 5 Pins [C6712C] IEEE-1149.1 (JTAG) Boundary-Scan-Compatible 256-Pin Ball Grid Array (BGA) Package (GFN Suffix) [C6712 Only] 272-Pin Ball Grid Array (BGA) Package (GDP Suffix) [C6712C Only] CMOS Technology - 0.13-m/6-Level Copper Metal Process - 0.18-m/5-Level Metal Process (C6712) 3.3-V I/Os, 1.26-V Internal (C6712C) 3.3-V I/Os, 1.8-V Internal (C6712)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320C67x, VelociTI, and C67x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. Other trademarks are the property of their respective owners. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

GFN BGA package (bottom view) [C6712 only]. 3 GDP BGA package (bottom view) [C6712C only]. 3 description. 4 device characteristics. 5 device compatibility. 6 functional block and CPU (DSP core) diagram. 7 CPU (DSP core) description. 8 memory map summary. 10 peripheral register descriptions. 11 signal groups description. 16 device configurations. 18 terminal functions. 20 development support. 32 documentation support. 35 CPU CSR register description. 36 interrupt sources and interrupt selector [C6712 only]. 38 interrupt sources and interrupt selector [C6712C only]. 39 EDMA channel synchronization events [C6712 only]. 40 EDMA module and EDMA selector [C6712C only]. 41 clock PLL [C6712 only]. 43 PLL and PLL controller [C6712C only]. 45 general-purpose input/output (GPIO). 52 power-supply sequencing. 53 power-supply decoupling. 54 IEEE 1149.1 JTAG compatibility statement. 54 EMIF device speed. 55 bootmode. absolute maximum ratings over operating case temperature range. recommended operating conditions. electrical characteristics over recommended ranges of supply voltage and operating case temperature.

parameter measurement information. 59 signal transition levels. 60 timing parameters and board routing analysis. 60 input and output clocks. 62 asynchronous memory timing. 67 synchronous-burst memory timing. 70 synchronous DRAM timing. 72 HOLD/HOLDA timing. 78 BUSREQ timing. 79 reset timing [C6712]. 80 reset timing [C6712C]. 82 external interrupt timing. 84 multichannel buffered serial port timing. 85 timer timing. 99 general-purpose input/output (GPIO) port timing [C6712C only]. 100 JTAG test-port timing. 101 mechanical data [C6712 only]. 102 mechanical data [C6712C only]. 103 revision history. 104

GFN 256-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW )
GDP 272-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW

 

Related products with the same datasheet
TMX320C6712CGDP
Some Part number from the same manufacture Texas Instruments, Inc.
TMS320C6712GFN100 ti TMS320C6712, Floating-point Digital Signal Processor
TMS320C6713 Floating-point Digital Signal Processor.<<<>>>the TMS320C67x DSPS (including The TMS320C6713 And TMS320C6713B Devices) Compose The Floating-point DSP Generation in The TMS320C6000 DSP Platform. The C6713
TMS320C6713-150
TMS320C6713BGDP225 Floating-point Digital Signal Processor.<<<>>>the TMS320C67x DSPS (including The TMS320C6713 And TMS320C6713B Devices) Compose The Floating-point DSP Generation in The TMS320C6000 DSP Platform. The C6713
TMS320C6713GDP225 ti TMS320C6713, Floating-point Digital Signal Processor
TMS320C6713GDPA200 Floating-point Digital Signal Processor.<<<>>>the TMS320C67x DSPS (including The TMS320C6713 And TMS320C6713B Devices) Compose The Floating-point DSP Generation in The TMS320C6000 DSP Platform. The C6713
TMS320C6713GDPA200 ti TMS320C6713, Floating-point Digital Signal Processor
TMS320C6713PYP200 Floating-point Digital Signal Processor.<<<>>>the TMS320C67x DSPS (including The TMS320C6713 And TMS320C6713B Devices) Compose The Floating-point DSP Generation in The TMS320C6000 DSP Platform. The C6713
TMS320C6713PYP200 ti TMS320C6713, Floating-point Digital Signal Processor
TMS320C80 Digital Signal Processor
TMS320C80GF ti TMS320C80, Multimedia Video Processor
TMS320C82 Digital Signal Processor
TMS320C82GGP50 ti TMS320C82, Multimedia Video Processor
TMS320DM640 Video/imaging Fixed-point Digital Signal Processor<<<>>>high-performance Digital Media Processor (TMS320DM641/TMS320DM640) <<<>>>2.5-, 2-, 1.67-ns Instruction Cycle Time <<<>>>400-, 500-, 600-MHz Clock
TMS320DM640 Video/imaging Fixed-point Digital Signal Processor<<<>>>the TMS320C64x TMS320DM640 Devices) Are The Highest-performance Fixed-point DSP Generation in The TMS320C6000 DSP Platform. The TMS320DM641 And TMS320DM640
TMS320DM640GDK400 Video/imaging Fixed-point Digital Signal Processor<<<>>>high-performance Digital Media Processor (TMS320DM641/TMS320DM640) <<<>>>2.5-, 2-, 1.67-ns Instruction Cycle Time <<<>>>400-, 500-, 600-MHz Clock
TMS320DM640GDK400 Video/imaging Fixed-point Digital Signal Processor<<<>>>the TMS320C64x TMS320DM640 Devices) Are The Highest-performance Fixed-point DSP Generation in The TMS320C6000 DSP Platform. The TMS320DM641 And TMS320DM640
TMS320DM640GNZ400 Video/imaging Fixed-point Digital Signal Processor<<<>>>high-performance Digital Media Processor (TMS320DM641/TMS320DM640) <<<>>>2.5-, 2-, 1.67-ns Instruction Cycle Time <<<>>>400-, 500-, 600-MHz Clock
TMS320DM640GNZ400 Video/imaging Fixed-point Digital Signal Processor<<<>>>the TMS320C64x TMS320DM640 Devices) Are The Highest-performance Fixed-point DSP Generation in The TMS320C6000 DSP Platform. The TMS320DM641 And TMS320DM640
TMS320DM641 Video/imaging Fixed-point Digital Signal Processor <<<>>>High-Performance Digital Media Processor (TMS320DM641/TMS320DM640) <<<>>>2.5-, 2-, 1.67-ns Instruction Cycle Time <<<>>>400-, 500-, 600-MHz Clock
TMS320DM641 Video/imaging Fixed-point Digital Signal Processor<<<>>>the TMS320C64x TMS320DM640 Devices) Are The Highest-performance Fixed-point DSP Generation in The TMS320C6000 DSP Platform. The TMS320DM641 And TMS320DM640
Same catergory

ADSP-21161N : Low-cost Sharc, 100 Mhz, 600 Mflops, 3.3 V I/O, 1.8 Volt Core, 32/40 Bit Floating Point, 32 Bit Fixed Point.

HMA510/883 : DSP Block. 16 X 16-Bit CMOS Parallel Multiplier Accumulator. The is a high speed, low power CMOS x 16-bit parallel multiplier accumulator capable of operating at 55ns clocked multiply-accumulate cycles. The 16-bit X and Y operands may be specified as either two's complement or unsigned magnitude format. Additional inputs are provided for the accumulator functions which include: loading the accumulator with the current.

HSP45256/883 : DSP Block. Binary Correlator. The Intersil is a high-speed, 256 tap binary correlator. It can be configured to perform one-dimensional or two-dimensional correlations of selectable data precision and length. Multiple HSP45256's can be cascaded for increased correlation length. Unused taps can be masked out for reduced correlation length. The correlation array consists of eight 32-tap.

PDSP16256 : Digital Filtering. = Programmable FIR Filter ;; Package Type = Pga ;; No. Of Pins = 144.

TMS320BC57SPGE57 : TMS320 Family->TMS320C5X Fixed Point DSP. ti TMS320BC57S, Digital Signal Processors.

TMS320C30 : TMS320 Family. Digital Signal Processor. High-Performance Floating-Point Digital Signal Processor (DSP) V) 40-ns Instruction Cycle Time 275 MOPS, 50 MFLOPS, 25 MIPS V) 50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS V) 60-ns Instruction Cycle Time 183.3 MOPS, 33.3 MFLOPS, 16.7 MIPS V) 74-ns Instruction Cycle Time 148.5 MOPS, 27 MFLOPS, 13.5 MIPS 32-Bit High-Performance CPU / 32-Bit.

TMS320C6205DGHK200 : TMS320 Family. ti TMS320C6205, Fixed-point Digital Signal Processor. Signal Processor (DSP) 5-ns Instruction Cycle Time 200-MHz Clock Rate Eight 32-Bit Instructions/Cycle 1600 MIPS VelociTI Advanced-Very-Long-InstructionWord (VLIW) TMS320C62x DSP Core Eight Highly Independent Functional Units: Six ALUs (32-/40-Bit) Two 16-Bit Multipliers (32-Bit Result) Load-Store Architecture With 32 32-Bit General-Purpose.

TMS320C6711 : 320 Family. Floating-point Digital Signal Processor. Processors (DSPs): (TMS320C6711, C6711B, and C6711C) Eight 32-Bit Instructions/Cycle 200-MHz Clock Rates 5-ns Instruction Cycle Time MFLOPS VelociTI Advanced Very Long Instruction Word (VLIW) C67x DSP Core Eight Highly Independent Functional Units: Four ALUs (Floating- and Fixed-Point) Two ALUs (Fixed-Point) Two Multipliers (Floating- and Fixed-Point).

TMS320C82GGP50 : TMS320 Family->TMS320C8X Multiprocessor DSP. ti TMS320C82, Multimedia Video Processor.

TMS320LC50PQ : TMS320 Family->TMS320C5X Fixed Point DSP. ti TMS320LC50, Digital Signal Processors.

TMS320P17FNA : TMS320 Family->TMS320C1X Fixed Point DSP. ti TMS320P17, Digital Signal Processors.

TMS320VC5420-200 : TMS320 Family. Independent Subsystems Each Core Has an Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Bus 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel-Shifter and Two 40-Bit Accumulators Per Core Each Core Has 17-Bit Parallel Multiplier Coupled a 40-Bit Adder for Non-Pipelined Single-Cycle Multiply/ Accumulate.

TMS320DM642 : Video/Imaging Fixed-Point Digital Signal Processor The TMS320C64x DSPs (including the TMS320DM642 device) are the highest-performance fixed-point DSP generation in the TMS320C6000 DSP platform. The TMS320DM642 (DM642) device is based on the second-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture (VelociTI.2).

MC56F8356 : The 56F8356 and 56F8156 are members of the 56800E core-based family of controllers. Each combines, on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility,.

TMS320VC5505 : Low-Power Fixed-Point Digital Signal Processor The TMS320VC5505 is a member of TI\'s TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications. The TMS320VC5505 fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high.

TMS320C5534 : Fixed-Point Digital Signal Processor These devices are members of TI\'s TMS320C5000 fixed-point Digital Signal Processor (DSP) product family and are designed for low-power applications. The fixed-point DSP is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased.

 
0-C     D-L     M-R     S-Z