Details, datasheet, quote on part number: TMS320C6713-150
PartTMS320C6713-150
CategoryDSPs (Digital Signal Processors) => TMS320 Family
TitleTMS320 Family
Description
CompanyTexas Instruments, Inc.
DatasheetDownload TMS320C6713-150 datasheet
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Features, Applications

Signal Processor (DSP): TMS320C6713 Eight 32-Bit Instructions/Cycle 32/64-Bit Data Word 225-, 200-MHz (GDP), and 200-, 167-MHz (PYP) Clock Rates 5-, 6-Instruction Cycle Times and 1336 /1000 MIPS /MFLOPS Rich Peripheral Set, Optimized for Audio Highly Optimized C/C++ Compiler VelociTI Advanced Very Long Instruction Word (VLIW) TMS320C67x DSP Core Eight Independent Functional Units: Two ALUs (Fixed-Point) Four ALUs (Floating- and Fixed-Point) Two Multipliers (Floating- and Fixed-Point) Load-Store Architecture With 32 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size All Instructions Conditional Instruction Set Features Native Instructions for IEEE 754 Single- and Double-Precision Byte-Addressable 16-, 32-Bit Data) 8-Bit Overflow Protection Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization L1/L2 Memory Architecture 4K-Byte L1P Program Cache (Direct-Mapped) 4K-Byte L1D Data Cache 256K-Byte L2 Memory Total: 64K-Byte L2 Unified Cache/Mapped RAM, and 192K-Byte Additional L2 Mapped RAM Device Configuration Boot Mode: HPI, 16-, 32-Bit ROM Boot Endianness: Little Endian, Big Endian 32-Bit External Memory Interface (EMIF) Glueless Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM 512M-Byte Total Addressable External Memory Space Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)

D 16-Bit Host-Port Interface (HPI) D Two Multichannel Audio Serial Ports

(McASPs) Two Independent Clock Zones Each (1 TX and 1 RX) Eight Serial Data Pins Per Port: Individually Assignable to any of the Clock Zones Each Clock Zone Includes: Programmable Clock Generator Programmable Frame Sync Generator TDM Streams From 2-32 Time Slots Support for Slot Size: Bits Data Formatter for Bit Manipulation Wide Variety of I2S and Similar Bit Stream Formats Integrated Digital Audio Interface Transmitter (DIT) Supports: S/PDIF, AES-3, CP-430 Formats to 16 transmit pins Enhanced Channel Status/User Data Extensive Error Checking and Recovery Two Inter-Integrated Circuit Bus (I2C Bus) Multi-Master and Slave Interfaces Two Multichannel Buffered Serial Ports: Serial-Peripheral-Interface (SPI) High-Speed TDM Interface AC97 Interface Two 32-Bit General-Purpose Timers Dedicated GPIO Module With 16 pins (External Interrupt Capable) Flexible Phase-Locked-Loop (PLL) Based Clock Generator Module IEEE-1149.1 (JTAG) Boundary-Scan-Compatible Package Options: 208-Pin PowerPAD Plastic (Low-Profile) Quad Flatpack (PYP) 272-Ball, Ball Grid Array Package (GDP) 0.13-m/6-Level Copper Metal Process CMOS Technology 3.3-V I/Os, 1.2-V Internal (PYP) 3.3-V I/Os, 1.26-V Internal (GDP)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320C67x, VelociTI, and PowerPAD are trademarks of Texas Instruments. I2C Bus is a trademark of Philips Electronics N.V. Corporation All trademarks are the property of their respective owners. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

GDP 272-Ball BGA package (bottom view). 3 PYP PowerPAD QFP package (top view). 8 description. 9 device characteristics. 10 functional block and CPU (DSP core) diagram. 11 CPU (DSP core) description. 12 memory map summary. 14 peripheral register descriptions. 16 signal groups description. 25 device configurations. 30 configuration examples. 37 debugging considerations. 44 terminal functions. 45 development support. 61 documentation support. 64 CPU CSR register description. 65 interrupts and interrupt selector. 67 external interrupt sources. 69 EDMA module and EDMA selector. 70 PLL and PLL controller. 73 multichannel audio serial port (McASP) peripherals. I2C. 85 power-supply sequencing. 86 power-supply decoupling. 86 IEEE 1149.1 JTAG compatibility statement. 87 EMIF device speed. 87 bootmode. absolute maximum ratings over operating case temperature range. recommended operating conditions. electrical characteristics over recommended ranges of supply voltage and operating case temperature.

parameter measurement information. 91 signal transition levels. 91 timing parameters and board routing analysis. 92 input and output clocks. 94 asynchronous memory timing. 97 synchronous-burst memory timing. 100 synchronous DRAM timing. 102 HOLD/HOLDA timing. 108 BUSREQ timing. 109 reset timing. 110 external interrupt timing. 112 multichannel audio serial port (McASP) timing. 113 inter-integrated circuits (I2C) timing. 116 host-port interface timing. 118 multichannel buffered serial port timing. 121 timer timing. 132 general-purpose input/output (GPIO) port timing. 133 JTAG test-port timing. 134 mechanical data. 135 revision history. 138

Y VSS ED18 BE2 ARDY EA2 DVDD EA7 EA9 ECLKOUT AOE/ SDRAS/ SSOE ECLKIN CLKOUT2/ GP[2] VSS EA16 EA18 DVDD EA20 VSS








Shading denotes the GDP package pin functions that drop out on the PYP package.

 

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