Details, datasheet, quote on part number: TMS320C6713GDPA200
PartTMS320C6713GDPA200
CategorySemiconductors => Processors => Digital Signal Processors => C6000 DSP => Other C6000 DSP
Part familyTMS320C6713 Floating-Point Digital Signal Processor
TitleTMS320 Family
DescriptionFloating-Point Digital Signal Processor 272-BGA
CompanyTexas Instruments, Inc.
StatusOBSOLETE
ROHSNot Compliant
SampleNo
DatasheetDownload TMS320C6713GDPA200 datasheet
Quote
Find where to buy
 
  
  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
272GDPBGAS-PBGA-N 27271.781.27
Application notes
• Using the ADS8327 with the TMS320C6713 DSP
This application report presents one solution for interfacing the ADS8327 16-bit, 500-KSPS serial interface converter to the TMS320C6713 digital signal processor (DSP). The hardware solution comprises the ADS8327EVM, TMS320C6713 DSP Starter Kit (DSK), and | Doc
• TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A)
Interfacing external asynchronous static RAM (ASRAM) to the Texas Instruments (TI™) TMS320C6000 series of digital signal processors (DSPs) is simple compared to previous generations of TI DSPs, thanks to the advanced external memory interface (EMIF). The | Doc
• TMS320C6000 EMIF to External Flash Memory (Rev. A)
Interfacing external flash memory to the Texas Instruments TMS320C6000™ digital signal processor (DSP) is simple compared to previous generations of TI DSPs. The TMS320C6000 advanced external memory interface (EMIF) provides a glueless interface to a var | Doc
• TMS320C621x/TMS320C671x EDMA Architecture
The enhanced DMA (EDMA) controller of the TMS320C621x™/TMS320C671x™ device is a highly efficient data transfer engine. To maximize bandwidth, minimize transfer interference, and fully utilize the resources of the EDMA, it is crucial to understand the a | Doc
• Interfacing the ADS8402/ADS8412 to TMS320C6713 DSP
This application report presents a solution for interfacing the ADS8402 and ADS8412 16-bit, parallel interface converters to the TMS320C6713 DSP. The hardware solution consists of existing and orderable hardware, specifically the ADS8402EVM, 'C6713 DSK, an | Doc
• TMS320C6000 C Compiler: C Implementation of Intrinsics
The first optimization step that you can perform on C source code for the TMS320C62xx is to use intrinsic operators. Intrinsics are used like functions and produce assembly language statements that would otherwise be inexpressible in C. The problem is that | Doc
• Using IBIS Models for Timing Analysis (Rev. A)
Today?s high-speed interfaces require strict timings and accurate system design. To achieve the necessary timings for a given system, input/output buffer information specification (IBIS) models must be used. These models accurately represent the device dri | Doc
• TMS320C6000 McBSP: IOM-2 Interface (Rev. A)
This document describes how the multi-channel buffered serial port (McBSP) in the Texas Instruments (TI) TMS320C6000? (C6000?) digital signal processor (DSP) family is used to communicate to an ISDN Oriented Modular Interface Revision 2 (IOM-2) bus-complia | Doc
• TMS320C6000 Board Design: Considerations for Debug (Rev. C) | Doc
• How to Begin Development Today with the TMS320C6713 Floating-Point DSP (Rev. A)
Development can begin now for the Texas Instruments TMS320C6713 highest-performance, peripheral-rich floating-point digital signal processor (DSP) systems. Because of the compatibility between TMS320C6000?DSP platform devices, existing C6000?so | Doc
• TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A)
This application report describes the interface between the Texas Instruments (TI) TMS320C6000™ digital signal processor (DSP) host port and the Intel 80960 microprocessor. The document includes schematics showing connections between the two devices, PAL | Doc
• TMS320C6000 DMA Example Applications (Rev. A)
The TMS320C6000? on-chip direct memory access (DMA) controller from Texas Instruments is used to transfer data between two locations in the memory map in the background of CPU operation. Typically, the DMA is used to:Transfer blocks of data between externa | Doc
• TMS320C6000 McBSP: Interface to SPI ROM (Rev. C)
The TMS320C6000? (C6000?) Multichannel Buffered Serial Port (McBSP) is designed to interface to a device that supports synchronous Serial Peripheral Interface (SPI). This document describes the hardware interface between the McBSP and a SPI ROM. The McBSP | Doc
• TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E)
Interfacing external SDRAM to the Texas Instruments TMS320C6000™ digital signal processor (DSP) is simple, compared to previous generations of TI DSPs, because of the advanced external memory interface (EMIF). The EMIF is a glueless interface to a variet | Doc
• TMS320C6713 Hardware Designer's Resource Guide
The DSP Hardware Designer's Resource Guide is organized by development flow and functional areas to make your design effort as seamless as possible. Topics covered includegetting started, board design, system testing, and checklists to aid in your initial | Doc
• Interfacing the ADS8401/ADS8411 to TMS320C6713 DSP
This application report presents a solution for interfacing the ADS8401 and ADS8411 16-bit, parallel interface converters to the TMS320C6713 DSP. The hardware solution consists of existing hardware, specifically the ADS8411EVM, 'C6713 DSK, and 5-6K interfa | Doc
• TMS320C6000 Enhanced DMA: Example Applications (Rev. A)
The enhanced direct memory access (EDMA) controller is the backbone of the two-level cache architecture for the TMS320C6000? DSPs. The EDMA performs:o cache servicingo host-port servicingo user-programmable data transfers Through proper configuration, EDMA | Doc
• TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D)
Texas Instruments TMS320C6000™ digital signal processors (DSPs) provide a variety of boot configurations that determine which actions are performed after device reset, to prepare for initialization. The boot process is determined by latching the boot con | Doc
• TMS320C6000 Host Port to MPC860 Interface (Rev. A)
This application report describes an interface between the Motorola MPC860 microprocessor and the host port interface (HPI) of a Texas Instruments TMS320C6000™ (C6000™) digital signal processor (DSP) device. This document includes a schematic showing c | Doc
• TMS320C621x/671x EDMA Performance Data
The enhanced DMA (EDMA) controller of the TMS320C621x™/TMS320C671x™ devices is a highly efficient data transfer engine, capable of maintaining transfers at up to 1800 MB/sec at a 225 MHz CPU clock frequency. This document details actual bandwidth achie | Doc
• Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A)
This document describes how to use the mulit-channel buffered serial ports (McBSP) in the Texas Instruments (TI) TMS320C6000™ digital signal processor (DSP) as a high-speed data communication port.One McBSP of one C6000™ DSP device can be connected to | Doc
• TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A)
This document describes how to interface the multichannel buffered serial port (McBSP) in the TMS320C6000? digital signal processor (DSP) to a voice band audio processor (VBAP). The VBAP under discussion is the TI TLV320AC56, 3V, 2.048 MHz audio processo | Doc
• Interfacing the ADS7881 to TMS320C6713 DSP
This application report presents a solution to interfacing the ADS7881 12-bit parallel interface converter to the TMS320C6713 DSP. The hardware solution is made up of existing hardware, specifically, the ADS7881EVM, 'C6713 DSK, and the 5-6K Interface Board | Doc
• TMS320C6000 McBSP: I2S Interface
This document describes how to use the multichannel buffered serial port (McBSP) in the Texas Instruments (TI)(TM) TMS320C6000 digital signal processors (DSP) to interface with devices that conform to the Inter-IC Sound (I2S) specification. I2S is a proto | Doc
• Migrating from TMS320C6211B/C6711/C6711B and C6713 to TMS320C6713B (Rev. H)
This document describes issues of interest related to migration from the Texas Instruments TMS320C6211B/C6711/C6711B GFN package and TMS320C6713 GDP package to the TMS320C6713B digital signal processor (DSP) GDP package. The objective of this document is t | Doc
• TMS320C6000 u-Law and a-Law Companding with Software or the McBSP
This document describes how to perform data companding with the TMS320C6000(tm)digital signal processors(DSP). Companding refers to the compression and expansion of transfer data before and after transmission, respectively.The multichannel buffered serial | Doc
• TMS320C6000 McBSP as a TDM Highway (Rev. A)
This document describes how the multichannel buffered serial ports (McBSP) in the TMS320C6000™ digital signal processors (DSP) are used to communicate on a time-division multiplexed (TDM) data highway.TDM provides multiple devices a time slot to perform | Doc
• TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B)
This document describes how the multichannel buffered serial ports (McBSPs) in the Texas Instruments TMS320C6000™ digital signal processor (DSP) are used to communicate to a single-rate Serial Telecom (ST)-BUS-compliant device.The McBSP receives the fram | Doc
• TMS320C6000 System Clock Circuit Example (Rev. A)
This document describes how to provide the Texas Instruments TMS320C6000™ DSP with a system clock. All of the clocks internal to the C6000™ are generated from a single source through the CLKIN pin. This source clock for the device is an external signal | Doc
• A DSP/BIOS AIC23 Codec Device Driver for the TMS320C6713 DSK | Doc
• TMS320C621x/C671x EDMA Queue Management Guidelines
The enhanced DMA (EDMA) controller of the TMS320C621x and TMS320C671x devices is a highly efficient data transfer engine, controlling all of the data movement beyond the level-two memory of the device. There are sixteen channels and a quick DMA (QDMA) avai | Doc
• TMS320C6000 Board Design for JTAG (Rev. C)
Designing a TMS320C6000™ DSP board to utilize all of the functionality of the JTAG scan path is a simple process, but a few considerations must be taken into account. The default state of the emulation signals determines whether the JTAG port is used for | Doc
• TMS320C6000 McBSP Initialization (Rev. C)
The TMS320C6000? multichannel buffered serial port (McBSP) can operate in a variety of modes, as per application requirements. For proper operation, the serial port must be initialized in a specific order. This document describes the initialization steps n | Doc
• TMS320C6713 to TMS320C672x Migration Guide | Doc
• TMS320C6711D, C6712D, C6713B Power Consumption Summary (Rev. A)
This document discusses the power consumption of the Texas Instruments TMS320C6711D, TMS320C6712D, and TMS320C6713B digital signal processors (DSPs). Power consumption on these devices is highly application dependent, so a spreadsheet is provided to model | Doc
• Using a TMS320C6000 McBSP for Data Packing (Rev. A)
This application report describes how to use the multichannel buffered serial port (McBSP) in the Texas Instruments TMS320C6000™ digital signal processor (DSP) for data packing. Data packing involves moving either multiple successive 8-bit elements to/f | Doc
• TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C)
This application report describes an interface between the Texas Instruments TMS320C6000™ DSP host port and the PLX Technology PCI9050 (PCI9052), the PCI interface chip. The PCI9052 is functionally the same as the PCI9050. The only difference between the | Doc
• Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A)
This application report describes the architecture and capabilities of the AMCC S5933 PCI controller and how it can be interfaced to the TMS320C6201 digital signal processor (DSP). The DSP's host port interface (HPI) can be a PCI target, and its external m | Doc
• TMS320C6000 Host Port to MC68360 Interface (Rev. A)
This application report describes an interface between the Motorola MC68360 quad integrated communication controller (QUICC) and the host port interface (HPI) of a TMS320C6000™ (C6000™) digital signal processor (DSP) device. This includes a schematic s | Doc
• Using the ADS8380 with the TMS320C6713 DSP
This application report presents a solution to interfacing the ADS8380 18-bit, 600-KSPS serial interface converter to the TMS320C6713 DSP. The hardware solution is made up of existing hardware: the ADS8380EVM, 'C6713 DSK, and 5-6K Interface Board. The soft | Doc
• Circular Buffering on TMS320C6000 (Rev. A)
This application report explains how circular buffering is implemented on the TMS320C6000? devices. Circular buffering helps to implement finite impulse response (FIR) filters efficiently. Filters require delay lines or buffers of past (and current) sample | Doc
• How to Begin Development Today w/ High Performance Floating Point TMS320C67x DSP
This application report describes how you can begin development now for the Texas Instruments (TI™) TMS320C67x generation of high-performance digital signal processors (DSPs). Because of the compatibility between TMS320C6000 generation devices, existing C | Doc
• PowerPAD™ Thermally Enhanced Package (Rev. G) | Doc
• TMS320C6713 DSP Optimized for High Performance Multichannel Audio Systems
The TMS320C6713?s high performance CPU and rich peripheral set are tailored for multichannel audio applications such as broadcast and recording mixing, home and large venue audio decoders, and multi-zone audio distribution. The TMS320C6713 device is based | Doc
• TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A)
This document describes how to use the multichannel buffered serial ports (McBSPs) in the Texas Instruments TMS320C6000™ digital signal processor (DSP) as a digital controller for an audio codec 1997 device.The McBSP is connected to a stereo audio codec | Doc
• TMS320C6000 EDMA IO Scheduling and Performance
The enhanced DMA (EDMA) is a highly efficient and parallel data transfer engine. To make the best use of its resources, it is necessary to understand the architecture and schedule transfers intelligently. This document details how to summarize, analyze, an | Doc
Evaluation Kits
TMDSDSK6713: TMS320C6713 DSP Starter Kit (DSK)

 

Features, Applications

Signal Processor (DSP): TMS320C6713 - Eight 32-Bit Instructions/Cycle - 32/64-Bit Data Word 225-, 200-MHz (GDP), and 200-, 167-MHz (PYP) Clock Rates 5-, 6-Instruction Cycle Times and 1336 /1000 MIPS /MFLOPS - Rich Peripheral Set, Optimized for Audio - Highly Optimized C/C++ Compiler VelociTI Advanced Very Long Instruction Word (VLIW) TMS320C67x DSP Core - Eight Independent Functional Units: - Two ALUs (Fixed-Point) - Four ALUs (Floating- and Fixed-Point) - Two Multipliers (Floating- and Fixed-Point) - Load-Store Architecture With 32 32-Bit General-Purpose Registers - Instruction Packing Reduces Code Size - All Instructions Conditional Instruction Set Features - Native Instructions for IEEE 754 - Single- and Double-Precision - Byte-Addressable 16-, 32-Bit Data) - 8-Bit Overflow Protection - Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization L1/L2 Memory Architecture 4K-Byte L1P Program Cache (Direct-Mapped) 4K-Byte L1D Data Cache 256K-Byte L2 Memory Total: 64K-Byte L2 Unified Cache/Mapped RAM, and 192K-Byte Additional L2 Mapped RAM Device Configuration - Boot Mode: HPI, 16-, 32-Bit ROM Boot - Endianness: Little Endian, Big Endian 32-Bit External Memory Interface (EMIF) - Glueless Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM - 512M-Byte Total Addressable External Memory Space Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)

D 16-Bit Host-Port Interface (HPI) D Two Multichannel Audio Serial Ports

(McASPs) - Two Independent Clock Zones Each (1 TX and 1 RX) - Eight Serial Data Pins Per Port: Individually Assignable to any of the Clock Zones - Each Clock Zone Includes: - Programmable Clock Generator - Programmable Frame Sync Generator - TDM Streams From 2-32 Time Slots - Support for Slot Size: Bits - Data Formatter for Bit Manipulation - Wide Variety of I2S and Similar Bit Stream Formats - Integrated Digital Audio Interface Transmitter (DIT) Supports: - S/PDIF, AES-3, CP-430 Formats to 16 transmit pins - Enhanced Channel Status/User Data - Extensive Error Checking and Recovery

Multi-Master and Slave Interfaces Two Multichannel Buffered Serial Ports: - Serial-Peripheral-Interface (SPI) - High-Speed TDM Interface - AC97 Interface Two 32-Bit General-Purpose Timers Dedicated GPIO Module With 16 pins (External Interrupt Capable) Flexible Phase-Locked-Loop (PLL) Based Clock Generator Module IEEE-1149.1 (JTAG) Boundary-Scan-Compatible Package Options: - 208-Pin PowerPAD Plastic (Low-Profile) Quad Flatpack (PYP) - 272-Ball, Ball Grid Array Package (GDP) 0.13-m/6-Level Copper Metal Process - CMOS Technology 3.3-V I/Os, 1.2-V Internal (PYP) 3.3-V I/Os, 1.26-V Internal (GDP)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320C67x, VelociTI, and PowerPAD are trademarks of Texas Instruments. I2C Bus is a trademark of Philips Electronics N.V. Corporation All trademarks are the property of their respective owners. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

GDP 272-Ball BGA package (bottom view). 3 PYP PowerPAD QFP package (top view). 8 description. 9 device characteristics. 10 functional block and CPU (DSP core) diagram. 11 CPU (DSP core) description. 12 memory map summary. 14 peripheral register descriptions. 16 signal groups description. 25 device configurations. 30 configuration examples. 37 debugging considerations. 44 terminal functions. 45 development support. 61 documentation support. 64 CPU CSR register description. 65 interrupts and interrupt selector. 67 external interrupt sources. 69 EDMA module and EDMA selector. 70 PLL and PLL controller. 73 multichannel audio serial port (McASP) peripherals. I2C. 85 general-purpose input/output (GPIO). 86 power-supply sequencing. 87 power-supply decoupling. 87 IEEE 1149.1 JTAG compatibility statement. 88 EMIF device speed. 89 bootmode. 90 absolute maximum ratings over operating case temperature range. 91 recommended operating conditions. 91 electrical characteristics over recommended ranges of supply voltage and operating case temperature. 92 parameter measurement information. 93 signal transition levels. 93 timing parameters and board routing analysis. 94 input and output clocks. 96 asynchronous memory timing. 99 synchronous-burst memory timing. 102 synchronous DRAM timing. 104 HOLD/HOLDA timing. 110 BUSREQ timing. 111 reset timing. 112 external interrupt timing. 114 multichannel audio serial port (McASP) timing. 115 inter-integrated circuits (I2C) timing. 118 host-port interface timing. 120 multichannel buffered serial port timing. 123 timer timing. 134 general-purpose input/output (GPIO) port timing. 135 JTAG test-port timing. 136 mechanical data. 137 revision history. 140









Shading denotes the GDP package pin functions that drop out on the PYP package.

 

Related products with the same datasheet
TMS320C6713PYP200
Some Part number from the same manufacture Texas Instruments, Inc.
TMS320C6713PYP200 Floating-point Digital Signal Processor.<<<>>>the TMS320C67x DSPS (including The TMS320C6713 And TMS320C6713B Devices) Compose The Floating-point DSP Generation in The TMS320C6000 DSP Platform. The C6713
TMS320C6713PYP200 ti TMS320C6713, Floating-point Digital Signal Processor
TMS320C80 Digital Signal Processor
TMS320C80GF ti TMS320C80, Multimedia Video Processor
TMS320C82 Digital Signal Processor
TMS320C82GGP50 ti TMS320C82, Multimedia Video Processor
TMS320DM640 Video/imaging Fixed-point Digital Signal Processor<<<>>>high-performance Digital Media Processor (TMS320DM641/TMS320DM640) <<<>>>2.5-, 2-, 1.67-ns Instruction Cycle Time <<<>>>400-, 500-, 600-MHz Clock
TMS320DM640 Video/imaging Fixed-point Digital Signal Processor<<<>>>the TMS320C64x TMS320DM640 Devices) Are The Highest-performance Fixed-point DSP Generation in The TMS320C6000 DSP Platform. The TMS320DM641 And TMS320DM640
TMS320DM640GDK400 Video/imaging Fixed-point Digital Signal Processor<<<>>>high-performance Digital Media Processor (TMS320DM641/TMS320DM640) <<<>>>2.5-, 2-, 1.67-ns Instruction Cycle Time <<<>>>400-, 500-, 600-MHz Clock
TMS320DM640GDK400 Video/imaging Fixed-point Digital Signal Processor<<<>>>the TMS320C64x TMS320DM640 Devices) Are The Highest-performance Fixed-point DSP Generation in The TMS320C6000 DSP Platform. The TMS320DM641 And TMS320DM640
TMS320DM640GNZ400 Video/imaging Fixed-point Digital Signal Processor<<<>>>high-performance Digital Media Processor (TMS320DM641/TMS320DM640) <<<>>>2.5-, 2-, 1.67-ns Instruction Cycle Time <<<>>>400-, 500-, 600-MHz Clock
TMS320DM640GNZ400 Video/imaging Fixed-point Digital Signal Processor<<<>>>the TMS320C64x TMS320DM640 Devices) Are The Highest-performance Fixed-point DSP Generation in The TMS320C6000 DSP Platform. The TMS320DM641 And TMS320DM640
TMS320DM641 Video/imaging Fixed-point Digital Signal Processor <<<>>>High-Performance Digital Media Processor (TMS320DM641/TMS320DM640) <<<>>>2.5-, 2-, 1.67-ns Instruction Cycle Time <<<>>>400-, 500-, 600-MHz Clock
TMS320DM641 Video/imaging Fixed-point Digital Signal Processor<<<>>>the TMS320C64x TMS320DM640 Devices) Are The Highest-performance Fixed-point DSP Generation in The TMS320C6000 DSP Platform. The TMS320DM641 And TMS320DM640
TMS320DM641
TMS320DM641GDK500 Video/imaging Fixed-point Digital Signal Processor <<<>>>High-Performance Digital Media Processor (TMS320DM641/TMS320DM640) <<<>>>2.5-, 2-, 1.67-ns Instruction Cycle Time <<<>>>400-, 500-, 600-MHz Clock
TMS320DM641GDK600 Video/imaging Fixed-point Digital Signal Processor<<<>>>the TMS320C64x TMS320DM640 Devices) Are The Highest-performance Fixed-point DSP Generation in The TMS320C6000 DSP Platform. The TMS320DM641 And TMS320DM640
TMS320DM641GNZ500 Video/imaging Fixed-point Digital Signal Processor <<<>>>High-Performance Digital Media Processor (TMS320DM641/TMS320DM640) <<<>>>2.5-, 2-, 1.67-ns Instruction Cycle Time <<<>>>400-, 500-, 600-MHz Clock
TMS320DM641GNZ500 Video/imaging Fixed-point Digital Signal Processor<<<>>>the TMS320C64x TMS320DM640 Devices) Are The Highest-performance Fixed-point DSP Generation in The TMS320C6000 DSP Platform. The TMS320DM641 And TMS320DM640
TMS320DM641GNZ600 Video/imaging Fixed-point Digital Signal Processor <<<>>>High-Performance Digital Media Processor (TMS320DM641/TMS320DM640) <<<>>>2.5-, 2-, 1.67-ns Instruction Cycle Time <<<>>>400-, 500-, 600-MHz Clock
TMS320DM642 Video/imaging Fixed-point Digital Signal Processor<<<>>>high-performance Digital Media Processor (TMS320DM642) <<<>>>2-, 1.67-, 1.39-ns Instruction Cycle Time <<<>>>500-, 600-, 720-MHz Clock Rate <<<>>>Eight
 
0-C     D-L     M-R     S-Z