Details, datasheet, quote on part number: TMS320C82GGP60
PartTMS320C82GGP60
CategoryDSPs (Digital Signal Processors) => TMS320 Family->TMS320C8X Multiprocessor DSP
TitleTMS320 Family->TMS320C8X Multiprocessor DSP
Descriptionti TMS320C82, Multimedia Video Processor
CompanyTexas Instruments, Inc.
DatasheetDownload TMS320C82GGP60 datasheet
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Features, Applications

Single Chip Parallel MIMD DSP Over 1.5 Billion RISC-like Operations per Second Master Processor (MP) - 32-Bit RISC Processor - IEEE-754 Floating Point - 4K-Byte Instruction Cache - 4K-Byte Data Cache Two Parallel Processors (PPs) - 32-Bit Advanced DSP Processors - 64-Bit Opcode Provides Many Parallel Operations per Cycle - 4K-Byte Instruction Cache, 4K-Byte Parameter RAM, and 8K Bytes of Data RAM per PP Transfer Controller (TC) - 64-Bit Data Transfers to 480M-Byte/s Transfer Rate - 32-Bit Addressing - Direct EDO DRAM/VRAM Interface - Direct SDRAM Interface - Dynamic Bus Sizing - Intelligent Queuing and Cycle Prioritization

Big or Little Endian Operation 44K Bytes of On-Chip RAM 4G-Byte Address Space 16.6 ns Cycle Time 3.3-V Operation IEEE 1149.1 Test Port (JTAG)

description

The is a single chip, MIMD (multiple instruction/multiple data) parallel processor capable of performing over 1.5 billion operations per second. It consists a 32-bit RISC Master Processor with a 120-MFlop IEEE Floating Point Unit, two 32-bit parallel-processing DSPs (PPs), and a Transfer Controller with to 480 Mbyte/sec transfer rate. All the processors are tightly coupled via an on-chip crossbar which provides shared access to on-chip RAM. This performance and programmability make the `C82 ideally suited for video, imaging, and high-speed telecommunication applications.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443

Figure 1. `C82 Block Diagram Showing Datapaths The `C82 Block Diagram shows the major components of the `C82: the Master Processor (MP), Parallel Processors (PPs), Transfer Controller (TC), and JTAG Emulation Interface. Shared access to on-chip. Each PP can RAMs is achieved through the Crossbar. Crossbar connections are represented by perform three accesses per cycle through its Local, Global, and Instruction ports. The MP can access two RAMs per cycle through its Crossbar/Data and Instruction ports and the TC can access one RAM through its crossbar interface. Thus, up to nine simultaneous accesses are supported in each cycle. Addresses can be changed every cycle, allowing the crossbar matrix to be changed on a cycle-by-cycle basis. Contention between processors for the same RAM in the same cycle is resolved by a round-robin priority scheme. In addition to the Crossbar, a 32-bit data path exists between the MP and the TC. This allows the MP to access TC control registers which are memory-mapped into the MP's memory space.

PIN NO. A25 A26 FUNCTION NC PIN NO. B25 B26 FUNCTION NC /DBEN VDD STATUS0 /CAS/DQM6 VSS VDD /CAS/DQM1 VSS /HACK CLKOUT LF CLKIN VDD /XPT3 VSS VDD /EINT1 /TRST EMU1 VDD AD29 NC PIN NO. C25 C26 FUNCTION NC /DDIN NC VDD VSS VDD /CAS/DQM2 /CAS/DQM0 VDD VSS VDD VSSPLL /HREQ /XPT0 /EINT3 TCK TDI EMU0 TDO AD30 NC VDD NC PIN NO. D25 D26 FUNCTION NC /TRG/CAS VSS STATUS1 /CAS/DQM7 VSS /CAS/DQM4 VDD VSS REQ VSS VDDPLL VSS /RESET /LINT4 /EINT2 TMS VSS VDD VSS NC AD28 VSS NC


 

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