Details, datasheet, quote on part number: TMS320DM641GDK500
PartTMS320DM641GDK500
CategoryDSPs (Digital Signal Processors)
DescriptionVideo/imaging Fixed-point Digital Signal Processor <<<>>>High-Performance Digital Media Processor (TMS320DM641/TMS320DM640) <<<>>>2.5-, 2-, 1.67-ns Instruction Cycle Time <<<>>>400-, 500-, 600-MHz Clock Rate <<<>>>Eight 32-Bit Instructions/cycle <<<>>>3200, 4000, 4800 Mips <<<>>>Fully Software-compatible With C64x <<<>>>VelociTI.2 Extensions to Velociti Advanced Very-long-instruction-word (VLIW) TMS320C64x DSP Core <<<>>>Eight Highly Independent Functional Units With VelociTI.2 Extensions: <<<>>>Six Alus (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic Per Clock Cycle <<<>>>Two Multipliers Support Four 16 X 16-Bit Multiplies (32-Bit Results) Per Clock Cycle or Eight 8 X 8-Bit Multiplies (16-Bit Results) Per Clock Cycle<<<>>>load-store Architecture With Non-aligned Support <<<>>>64 32-Bit General-purpose Registers <<<>>>Instruction Packing Reduces Code Size <<<>>>All Instructions Conditional<<<>>>instruction Set Features <<<>>>Byte-Addressable (8-/16-/32-/64-Bit Data) <<<>>>8-Bit Overflow Protection <<<>>>Bit-Field Extract, Set, Clear <<<>>>Normalization, Saturation, Bit-counting <<<>>>VelociTI.2 Increased Orthogonality<<<>>>L1/L2 Memory Architecture <<<>>>128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped) <<<>>>128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative) <<<>>>1M-Bit (128K-Byte) L2 Unified Mapped RAM/cache (Flexible RAM/cache Allocation)<<<>>>Endianess: Little Endian, Big Endian <<<>>>32-Bit External Memory Interface (EMIF) <<<>>>Glueless Interface to Asynchronous Memories (SRAM And EPROM) And Synchronous Memories (SDRAM, Sbsram, ZBT SRAM, And FIFO) <<<>>>1024M-Byte Total Addressable External Memory Space<<<>>>enhanced Direct-memory-access (EDMA) Controller (64 Independent Channels) <<<>>>10/100 Mb/s Ethernet Mac (EMAC) <<<>>>IEEE 802.3 Compliant <<<>>>Media Independent Interface (MII) <<<>>>8 Independent Transmit (TX) And 8 Independent Receive (RX) Channels<<<>>>management Data Input/output (MDIO) <<<>>>Two Configurable Video Ports (DM641) One Configurable Video Port (DM640) <<<>>>Providing a Glueless I/f to Common Video Decoder And Encoder Devices <<<>>>Supports Multiple Resolutions And Video Standards<<<>>>vcxo Interpolated Control Port (VIC) <<<>>>Supports Audio/video Synchronization<<<>>>host-port Interface (HPI) 16-Bit (DM641) <<<>>>Multichannel Audio Serial Port (McASP) <<<>>>Four Serial Data Pins <<<>>>Wide Variety of I2S And Similar Bit Stream Format <<<>>>Integrated Digital Audio I/f Transmitter Supports S/PDIF, IEC60958-1, AES-3, CP-430 Formats<<<>>>inter-integrated Circuit (I2C) Bus <<<>>>Two Multichannel Buffered Serial Ports <<<>>>Three 32-Bit General-purpose Timers <<<>>>Eight General-purpose I/o (GPIO) Pins <<<>>>Flexible PLL Clock Generator <<<>>>IEEE-1149.1 (JTAG) Boundary-scan-compatible <<<>>>548-Pin Ball Grid Array (BGA) Package (GDK Suffix), 0.8-mm Ball Pitch <<<>>>548-Pin Ball Grid Array (BGA) Package (GNZ Suffix), 1.0-mm Ball Pitch <<<>>>0.13-Ám/6-Level cu Metal Process (CMOS) <<<>>>3.3-V I/Os, 1.2-V Internal (-400, -500) <<<>>>3.3-V I/Os, 1.4-V Internal (-600)
CompanyTexas Instruments, Inc.
DatasheetDownload TMS320DM641GDK500 datasheet
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This data sheet revision history highlights the technical changes made to the SPRS222A device-specific data sheet to make an SPRS222B revision. Scope: Applicable updates to the C64x device family, specifically relating to the TMS320DM641/TMS320DM640 devices, have been incorporated. Changed DM641/DM640 device-specific information to the advance information (AI) stage of development. Highlights:

D Updated/changed timings for Electrical Characteristics, Input and Output Clocks Timing, AECLKIN;

Asynchronous Memory; Programmable Synchronous Interface; Synchronous DRAM; Multichannel Buffered Serial Port; and Video Port Timings D Corrected timing parameter signal descriptions to match terminal functions

ADDS/CHANGES/DELETES Global change: Changed all EMIF signal names to be specific to EMIFA Updated the EMAC/MDIO peripherals detailed descriptions, the EMAC Control Registers table, the EMAC Statistics Registers table, and the MDIO Registers table to support an EMAC module that has 8 Independent Transmit (TX) Channels and 1 Receive (RX) Channel and does not support receive quality of service (QOS).

Table 1-1, Characteristics of the DM641 Processor: Changed Product Status from "PP" to "AI" (Advance Information) Table 1-2, Characteristics of the DM640 Processor: Changed Product Status from "PP" to "AI" (Advance Information) Table 1-6, L2 Cache Registers (C64x): Split the "Reserved" row between hex address range 1FFC" Added the L2 EDMA Access Control Register (EDMAWEIGHT) to the hex address location 0184 1000 Device Configurations section, Peripheral Selection at Device Reset: Added "For proper DM641/DM640 device operation, the GP0[0] pin [M5] (IPD) must remain low at device reset." bullet JTAG ID Register Description section: Changed the JTAG ID register address location from "0x01B3 F008" Figure 2-9, Configuration Example A for (1 8-Bit Video Port McASP0 + VIC I2C0 + EMIF) [TBD Application]: Removed the shading from the "McBSP1" block; module is active Table 2-9, Terminal Functions: Updated/changed the following DM641/DM640 RSV SIGNAL NAMEs to include their TYPE, and IPD/IPU column information: E14 I IPD; I AC4 O/Z AD3 O/Z and AF3 O IPU Documentation Support section: Added the "TMS320DM64x Power Consumption Summary application report (literature number SPRA962)" reference Figure 2-12, External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode: Deleted "L2 Clock" from the /2 outputs


 

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TMS320DM641GDK600 Video/imaging Fixed-point Digital Signal Processor<<<>>>the TMS320C64x TMS320DM640 Devices) Are The Highest-performance Fixed-point DSP Generation in The TMS320C6000 DSP Platform. The TMS320DM641 And TMS320DM640
TMS320DM641GNZ500 Video/imaging Fixed-point Digital Signal Processor <<<>>>High-Performance Digital Media Processor (TMS320DM641/TMS320DM640) <<<>>>2.5-, 2-, 1.67-ns Instruction Cycle Time <<<>>>400-, 500-, 600-MHz Clock
TMS320DM641GNZ500 Video/imaging Fixed-point Digital Signal Processor<<<>>>the TMS320C64x TMS320DM640 Devices) Are The Highest-performance Fixed-point DSP Generation in The TMS320C6000 DSP Platform. The TMS320DM641 And TMS320DM640
TMS320DM641GNZ600 Video/imaging Fixed-point Digital Signal Processor <<<>>>High-Performance Digital Media Processor (TMS320DM641/TMS320DM640) <<<>>>2.5-, 2-, 1.67-ns Instruction Cycle Time <<<>>>400-, 500-, 600-MHz Clock
TMS320DM642 Video/imaging Fixed-point Digital Signal Processor<<<>>>high-performance Digital Media Processor (TMS320DM642) <<<>>>2-, 1.67-, 1.39-ns Instruction Cycle Time <<<>>>500-, 600-, 720-MHz Clock Rate <<<>>>Eight
TMS320DM642 Video/imaging Fixed-point Digital Signal Processor<<<>>>the TMS320C64x DSPS (including The TMS320DM642 Device) Are The Highest-performance Fixed-point DSP Generation in The TMS320C6000 DSP Platform. The TMS320DM642
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TMS320DM642GDK500 Video/imaging Fixed-point Digital Signal Processor<<<>>>high-performance Digital Media Processor (TMS320DM642) <<<>>>2-, 1.67-, 1.39-ns Instruction Cycle Time <<<>>>500-, 600-, 720-MHz Clock Rate <<<>>>Eight
TMS320DM642GDK500 Video/imaging Fixed-point Digital Signal Processor<<<>>>the TMS320C64x DSPS (including The TMS320DM642 Device) Are The Highest-performance Fixed-point DSP Generation in The TMS320C6000 DSP Platform. The TMS320DM642
TMS320DM642GDK500
TMS320DM642GDK600 Video/imaging Fixed-point Digital Signal Processor<<<>>>high-performance Digital Media Processor (TMS320DM642) <<<>>>2-, 1.67-, 1.39-ns Instruction Cycle Time <<<>>>500-, 600-, 720-MHz Clock Rate <<<>>>Eight
TMS320DM642GDK600 Video/imaging Fixed-point Digital Signal Processor<<<>>>the TMS320C64x DSPS (including The TMS320DM642 Device) Are The Highest-performance Fixed-point DSP Generation in The TMS320C6000 DSP Platform. The TMS320DM642
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TMS320DM642GDK720 Video/imaging Fixed-point Digital Signal Processor<<<>>>high-performance Digital Media Processor (TMS320DM642) <<<>>>2-, 1.67-, 1.39-ns Instruction Cycle Time <<<>>>500-, 600-, 720-MHz Clock Rate <<<>>>Eight
TMS320DM642GNZ500 Video/imaging Fixed-point Digital Signal Processor<<<>>>the TMS320C64x DSPS (including The TMS320DM642 Device) Are The Highest-performance Fixed-point DSP Generation in The TMS320C6000 DSP Platform. The TMS320DM642
TMS320DM642GNZ500
TMS320DM642GNZ600 Video/imaging Fixed-point Digital Signal Processor<<<>>>high-performance Digital Media Processor (TMS320DM642) <<<>>>2-, 1.67-, 1.39-ns Instruction Cycle Time <<<>>>500-, 600-, 720-MHz Clock Rate <<<>>>Eight
TMS320DM642GNZ600 Video/imaging Fixed-point Digital Signal Processor<<<>>>the TMS320C64x DSPS (including The TMS320DM642 Device) Are The Highest-performance Fixed-point DSP Generation in The TMS320C6000 DSP Platform. The TMS320DM642
TMS320DM642GNZ600
TMS320DM642GNZ720 Video/imaging Fixed-point Digital Signal Processor<<<>>>high-performance Digital Media Processor (TMS320DM642) <<<>>>2-, 1.67-, 1.39-ns Instruction Cycle Time <<<>>>500-, 600-, 720-MHz Clock Rate <<<>>>Eight
 
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