Details, datasheet, quote on part number: TMS320DM641GNZ500
PartTMS320DM641GNZ500
CategorySemiconductors => Processors => Digital Signal Processors => Media Processors => DaVinci Video Processors
Part familyTMS320DM641 Video/Imaging Fixed-Point Digital Signal Processor
DescriptionVideo/Imaging Fixed-Point Digital Signal Processor 548-FCBGA
CompanyTexas Instruments, Inc.
StatusOBSOLETE
ROHSNot Compliant
SampleNo
DatasheetDownload TMS320DM641GNZ500 datasheet
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PackagesFCBGA (GNZ) | 548
  
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Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
548GNZFCBGAS-PBGA-N 27272.21
Application notes
• TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A)
Interfacing external asynchronous static RAM (ASRAM) to the Texas Instruments (TI™) TMS320C6000 series of digital signal processors (DSPs) is simple compared to previous generations of TI DSPs, thanks to the advanced external memory interface (EMIF). The | Doc
• TMS320C6000 EMIF to External Flash Memory (Rev. A)
Interfacing external flash memory to the Texas Instruments TMS320C6000™ digital signal processor (DSP) is simple compared to previous generations of TI DSPs. The TMS320C6000 advanced external memory interface (EMIF) provides a glueless interface to a var | Doc
• TMS320C6000 C Compiler: C Implementation of Intrinsics
The first optimization step that you can perform on C source code for the TMS320C62xx is to use intrinsic operators. Intrinsics are used like functions and produce assembly language statements that would otherwise be inexpressible in C. The problem is that | Doc
• Using IBIS Models for Timing Analysis (Rev. A)
Today?s high-speed interfaces require strict timings and accurate system design. To achieve the necessary timings for a given system, input/output buffer information specification (IBIS) models must be used. These models accurately represent the device dri | Doc
• TMS320C6000 McBSP: IOM-2 Interface (Rev. A)
This document describes how the multi-channel buffered serial port (McBSP) in the Texas Instruments (TI) TMS320C6000? (C6000?) digital signal processor (DSP) family is used to communicate to an ISDN Oriented Modular Interface Revision 2 (IOM-2) bus-complia | Doc
• TMS320C6000 Board Design: Considerations for Debug (Rev. C) | Doc
• TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A)
This application report describes the interface between the Texas Instruments (TI) TMS320C6000™ digital signal processor (DSP) host port and the Intel 80960 microprocessor. The document includes schematics showing connections between the two devices, PAL | Doc
• Use and Handling of Semiconductor Packages With ENIG Pad Finishes | Doc
• TMS320C6000 McBSP: Interface to SPI ROM (Rev. C)
The TMS320C6000? (C6000?) Multichannel Buffered Serial Port (McBSP) is designed to interface to a device that supports synchronous Serial Peripheral Interface (SPI). This document describes the hardware interface between the McBSP and a SPI ROM. The McBSP | Doc
• TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E)
Interfacing external SDRAM to the Texas Instruments TMS320C6000™ digital signal processor (DSP) is simple, compared to previous generations of TI DSPs, because of the advanced external memory interface (EMIF). The EMIF is a glueless interface to a variet | Doc
• Cache Usage in High-Performance DSP Applications with the TMS320C64x
The TMS320C64x™, the newest member of the TMS320C6000™ (C6000™) family, is used in high-performance DSP applications. The C64x™ processes information at a rate of 4800 MIPs, while operating at a clock rate of 600 MHz. Processing data at these extre | Doc
• TMS320C6000 Enhanced DMA: Example Applications (Rev. A)
The enhanced direct memory access (EDMA) controller is the backbone of the two-level cache architecture for the TMS320C6000? DSPs. The EDMA performs:o cache servicingo host-port servicingo user-programmable data transfers Through proper configuration, EDMA | Doc
• TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D)
Texas Instruments TMS320C6000™ digital signal processors (DSPs) provide a variety of boot configurations that determine which actions are performed after device reset, to prepare for initialization. The boot process is determined by latching the boot con | Doc
• TMS320C6000 Host Port to MPC860 Interface (Rev. A)
This application report describes an interface between the Motorola MPC860 microprocessor and the host port interface (HPI) of a Texas Instruments TMS320C6000™ (C6000™) digital signal processor (DSP) device. This document includes a schematic showing c | Doc
• TMS320DM640/1 Hardware Designer's Resource Guide (Rev. A)
The DSP Hardware Designer's Resource Guide is organized by development flow and functional areas to make your design effort as seamless as possible. Topics covered include getting started, board design, system testing, and checklists to aid in your initial | Doc
• Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A)
This document describes how to use the mulit-channel buffered serial ports (McBSP) in the Texas Instruments (TI) TMS320C6000™ digital signal processor (DSP) as a high-speed data communication port.One McBSP of one C6000™ DSP device can be connected to | Doc
• TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A)
This document describes how to interface the multichannel buffered serial port (McBSP) in the TMS320C6000? digital signal processor (DSP) to a voice band audio processor (VBAP). The VBAP under discussion is the TI TLV320AC56, 3V, 2.048 MHz audio processo | Doc
• TMS320DM64x Power Consumption Summary (Rev. F)
This document discusses the power consumption of the Texas Instruments TMS320DM640, TMS320DM641, TMS320DM642, and TMS320DM643 digital signal processors (DSPs). Power consumption on these devices is highly application-dependent, so a spreadsheet is provided | Doc
• TMS320C6000 McBSP: I2S Interface
This document describes how to use the multichannel buffered serial port (McBSP) in the Texas Instruments (TI)(TM) TMS320C6000 digital signal processors (DSP) to interface with devices that conform to the Inter-IC Sound (I2S) specification. I2S is a proto | Doc
• Migrating from TMS320DM642/3/1/0 to the TMS320DM647/DM648 Device
This application report describes issues of interest related to migration from the TMS320DM642/3/1/0 to the TMS320DM648/7 device. The objective of this document is to indicate differences between the two device portfolios. Functions that are identical betw | Doc
• TMS320C6000 u-Law and a-Law Companding with Software or the McBSP
This document describes how to perform data companding with the TMS320C6000(tm)digital signal processors(DSP). Companding refers to the compression and expansion of transfer data before and after transmission, respectively.The multichannel buffered serial | Doc
• High Resolution Video Using the DM642 DSP and the THS8200 Driver (Rev. A)
The DM642 DSP has three 20-bit video ports capable of high definition (HD) display. The video ports can be programmed to follow HDTV standards, such as SMPTE274M and SMPTE296M. These HDTV standards follow a 4:2:2 convention where luminance and chrominance | Doc
• TMS320C6000 McBSP as a TDM Highway (Rev. A)
This document describes how the multichannel buffered serial ports (McBSP) in the TMS320C6000™ digital signal processors (DSP) are used to communicate on a time-division multiplexed (TDM) data highway.TDM provides multiple devices a time slot to perform | Doc
• TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B)
This document describes how the multichannel buffered serial ports (McBSPs) in the Texas Instruments TMS320C6000™ digital signal processor (DSP) are used to communicate to a single-rate Serial Telecom (ST)-BUS-compliant device.The McBSP receives the fram | Doc
• TMS320C6000 System Clock Circuit Example (Rev. A)
This document describes how to provide the Texas Instruments TMS320C6000™ DSP with a system clock. All of the clocks internal to the C6000™ are generated from a single source through the CLKIN pin. This source clock for the device is an external signal | Doc
• Interfacing an LCD Controller to a DM642 Video Port (Rev. B)
There is an increasing demand to bring video and image processing capabilities to devices like video IP phones, cellular phones, and personal data assistants (PDAs). The images are brought to the user on liquid crystal displays that usually use thin film t | Doc
• Introduction to TMS320C6000 DSP Optimization
The TMS320C6000™ Digital Signal Processors (DSPs) have many architectural advantages that make them ideal for computation-intensive real-time applications. However, to fully leverage the architectural features that C6000™ processors offer, code optimiz | Doc
• Thermal Considerations for the DM64xx, DM64x, and C6000 Devices
As integrated circuit (IC) components become more complex, the challenge of producing an end product with superior thermal performance increases. Thermal performance is a system level concern, impacted by IC packaging as well as by printed circuit board (P | Doc
• TMS320C6000 Board Design for JTAG (Rev. C)
Designing a TMS320C6000™ DSP board to utilize all of the functionality of the JTAG scan path is a simple process, but a few considerations must be taken into account. The default state of the emulation signals determines whether the JTAG port is used for | Doc
• TMS320C6000 McBSP Initialization (Rev. C)
The TMS320C6000? multichannel buffered serial port (McBSP) can operate in a variety of modes, as per application requirements. For proper operation, the serial port must be initialized in a specific order. This document describes the initialization steps n | Doc
• Using a TMS320C6000 McBSP for Data Packing (Rev. A)
This application report describes how to use the multichannel buffered serial port (McBSP) in the Texas Instruments TMS320C6000™ digital signal processor (DSP) for data packing. Data packing involves moving either multiple successive 8-bit elements to/f | Doc
• TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C)
This application report describes an interface between the Texas Instruments TMS320C6000™ DSP host port and the PLX Technology PCI9050 (PCI9052), the PCI interface chip. The PCI9052 is functionally the same as the PCI9050. The only difference between the | Doc
• Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A)
This application report describes the architecture and capabilities of the AMCC S5933 PCI controller and how it can be interfaced to the TMS320C6201 digital signal processor (DSP). The DSP's host port interface (HPI) can be a PCI target, and its external m | Doc
• TMS320C6000 Host Port to MC68360 Interface (Rev. A)
This application report describes an interface between the Motorola MC68360 quad integrated communication controller (QUICC) and the host port interface (HPI) of a TMS320C6000™ (C6000™) digital signal processor (DSP) device. This includes a schematic s | Doc
• Circular Buffering on TMS320C6000 (Rev. A)
This application report explains how circular buffering is implemented on the TMS320C6000? devices. Circular buffering helps to implement finite impulse response (FIR) filters efficiently. Filters require delay lines or buffers of past (and current) sample | Doc
• General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point
Modern audio and video compression algorithms usually take the advantage of logarithmic characteristics of human ears and eyes. This approach greatly reduces the redundancy in signals being processed. However, it poses a requirement on fixed-point DSPs to | Doc
• TMS320C64x to TMS320C64x+ CPU Migration Guide (Rev. A)
This document describes migration from the Texas Instruments TMS320C64x™ digital signal processor (DSP) to the TMS320C64x+™ DSP. The objective of this document is to indicate differences between the two cores and to briefly describe new features. Funct | Doc
• TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A)
This document describes how to use the multichannel buffered serial ports (McBSPs) in the Texas Instruments TMS320C6000™ digital signal processor (DSP) as a digital controller for an audio codec 1997 device.The McBSP is connected to a stereo audio codec | Doc
• TMS320C6000 EDMA IO Scheduling and Performance
The enhanced DMA (EDMA) is a highly efficient and parallel data transfer engine. To make the best use of its resources, it is necessary to understand the architecture and schedule transfers intelligently. This document details how to summarize, analyze, an | Doc
Evaluation Kits
TMDSEMU560V2STM-U: XDS560v2 System Trace USB Debug Probe
XDS560TRACE: XDS560 Trace Emulator
TMDSEMU200-U: XDS200 USB Debug Probe
TMDSDSK6416: TMS320C6416 DSP Starter Kit (DSK)
TMDSEVM642: DM642 Evaluation Module
TMDSEMU560V2STM-UE: XDS560v2 System Trace USB & Ethernet Debug Probe

 

Features, Applications

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This data sheet revision history highlights the technical changes made to the SPRS222A device-specific data sheet to make an SPRS222B revision. Scope: Applicable updates to the C64x device family, specifically relating to the TMS320DM641/TMS320DM640 devices, have been incorporated. Changed DM641/DM640 device-specific information to the advance information (AI) stage of development. Highlights:

D Updated/changed timings for Electrical Characteristics, Input and Output Clocks Timing, AECLKIN;

Asynchronous Memory; Programmable Synchronous Interface; Synchronous DRAM; Multichannel Buffered Serial Port; and Video Port Timings D Corrected timing parameter signal descriptions to match terminal functions

ADDS/CHANGES/DELETES Global change: Changed all EMIF signal names to be specific to EMIFA Updated the EMAC/MDIO peripherals detailed descriptions, the EMAC Control Registers table, the EMAC Statistics Registers table, and the MDIO Registers table to support an EMAC module that has 8 Independent Transmit (TX) Channels and 1 Receive (RX) Channel and does not support receive quality of service (QOS).

Table 1-1, Characteristics of the DM641 Processor: Changed Product Status from "PP" to "AI" (Advance Information) Table 1-2, Characteristics of the DM640 Processor: Changed Product Status from "PP" to "AI" (Advance Information) Table 1-6, L2 Cache Registers (C64x): Split the "Reserved" row between hex address range 1FFC" Added the L2 EDMA Access Control Register (EDMAWEIGHT) to the hex address location 0184 1000 Device Configurations section, Peripheral Selection at Device Reset: Added "For proper DM641/DM640 device operation, the GP0[0] pin [M5] (IPD) must remain low at device reset." bullet JTAG ID Register Description section: Changed the JTAG ID register address location from "0x01B3 F008" Figure 2-9, Configuration Example A for (1 8-Bit Video Port McASP0 + VIC I2C0 + EMIF) [TBD Application]: Removed the shading from the "McBSP1" block; module is active Table 2-9, Terminal Functions: Updated/changed the following DM641/DM640 RSV SIGNAL NAMEs to include their TYPE, and IPD/IPU column information: E14 I IPD; I AC4 O/Z AD3 O/Z and AF3 O IPU Documentation Support section: Added the "TMS320DM64x Power Consumption Summary application report (literature number SPRA962)" reference Figure 2-12, External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode: Deleted "L2 Clock" from the /2 outputs


 

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