Details, datasheet, quote on part number: TMS320DM642AGNZ5
PartTMS320DM642AGNZ5
CategorySemiconductors => Processors => Digital Signal Processors => Media Processors => DaVinci Video Processors
Part familyTMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor
DescriptionVideo/Imaging Fixed-Point Digital Signal Processor 548-FCBGA
CompanyTexas Instruments, Inc.
StatusNRND
ROHSNot Compliant
SampleNo
DatasheetDownload TMS320DM642AGNZ5 datasheet
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PackagesFCBGA (GNZ) | 548
  
  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
548GNZFCBGAS-PBGA-NTMS320DM642A 27272.21
Application notes
• TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A)
Interfacing external asynchronous static RAM (ASRAM) to the Texas Instruments (TI™) TMS320C6000 series of digital signal processors (DSPs) is simple compared to previous generations of TI DSPs, thanks to the advanced external memory interface (EMIF). The | Doc
• TMS320C6000 EMIF to External Flash Memory (Rev. A)
Interfacing external flash memory to the Texas Instruments TMS320C6000™ digital signal processor (DSP) is simple compared to previous generations of TI DSPs. The TMS320C6000 advanced external memory interface (EMIF) provides a glueless interface to a var | Doc
• MPEG-2 Encoder on the DM642 EVM
The software demonstrates real-time D1 MPEG-2 encoding on the DM642 EVM. The demonstration encodes the captured frames and displays all the frames from the reconstruction loop of the encoder.The demonstration uses:MPEG-2 encoder library optimized for DM642 | Doc
• Interfacing a CMOS Sensor to the TMS320DM642 Using Raw Capture Mode (Rev. A)
This document contains information on how to interface the TMS320DM642 to a CMOS Digital Image Sensor in raw capture mode. A complete example is shown, including hardware and software interfaces. The software consists of a set of routines that are compatib | Doc
• The TMS320DM642 Video Port Mini-Driver for TVP5146 and TVP5150 decoder
This application report describes the usage and design of the video capture mini−drivers that work on the TMS320DM642 Evaluation Module (EVM) with TVP5146 and TVP5150A decoders. Use this application report as well as The TMS320DM642 Video Port Mini−Dr | Doc
• TMS320C6000 C Compiler: C Implementation of Intrinsics
The first optimization step that you can perform on C source code for the TMS320C62xx is to use intrinsic operators. Intrinsics are used like functions and produce assembly language statements that would otherwise be inexpressible in C. The problem is that | Doc
• Using IBIS Models for Timing Analysis (Rev. A)
Today?s high-speed interfaces require strict timings and accurate system design. To achieve the necessary timings for a given system, input/output buffer information specification (IBIS) models must be used. These models accurately represent the device dri | Doc
• Audio Demonstration on the DM642 EVM
The software demonstrates a g.729a voice codec running on the DM642 EVM. The demonstration collects stereo samples and plays back the resulting samples. The right channel samples are not modified and fed straight through. The left channel samples are fed t | Doc
• TMS320C6000 McBSP: IOM-2 Interface (Rev. A)
This document describes how the multi-channel buffered serial port (McBSP) in the Texas Instruments (TI) TMS320C6000? (C6000?) digital signal processor (DSP) family is used to communicate to an ISDN Oriented Modular Interface Revision 2 (IOM-2) bus-complia | Doc
• TMS320C6000 Board Design: Considerations for Debug (Rev. C) | Doc
• MPEG-2 High Definition Decoder on the DM642 EVM
The software demonstrates the MPEG-2 high-definition (HD) decoder running on the DM642 Evaluation Module (EVM). The demonstration uses the MPEG-2 HD decoder to decode the MPEG-2 HD bitstream and display the decoded frames on the HD output device.The demons | Doc
• TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A)
This application report describes the interface between the Texas Instruments (TI) TMS320C6000™ digital signal processor (DSP) host port and the Intel 80960 microprocessor. The document includes schematics showing connections between the two devices, PAL | Doc
• Use and Handling of Semiconductor Packages With ENIG Pad Finishes | Doc
• TMS320C6000 McBSP: Interface to SPI ROM (Rev. C)
The TMS320C6000? (C6000?) Multichannel Buffered Serial Port (McBSP) is designed to interface to a device that supports synchronous Serial Peripheral Interface (SPI). This document describes the hardware interface between the McBSP and a SPI ROM. The McBSP | Doc
• Audio Echo on the DM642 EVM
The software demonstrates an audio loopback example on the DM642 EVM, with programmable echo added to the input signal. The demonstration creates and primes the audio I/O streams, initializes the echo buffer, enters a loop reading audio samples, then proce | Doc
• MPEG-2 Loop Back on the DM642 EVM
The software demonstrates the D1 MPEG-2 encoder and decoder running back-to-back on a DM642 Evaluation Module (EVM). The demonstration encodes the captured frames and then decodes the generated MPEG-2 bitstream to display the decoded frames.The demonstrati | Doc
• TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E)
Interfacing external SDRAM to the Texas Instruments TMS320C6000™ digital signal processor (DSP) is simple, compared to previous generations of TI DSPs, because of the advanced external memory interface (EMIF). The EMIF is a glueless interface to a variet | Doc
• TMS320DM642 to TMS320DM6467 Migration
This document describes device considerations to migrate a design based on a TI TMS320DM642 video/imaging fixed-point Digital Signal Processor (DSP) to one based on a TI TMS320DM6467 Digital Media System-on-Chip (DMSoC). These two devices are based on simi | Doc
• Cache Usage in High-Performance DSP Applications with the TMS320C64x
The TMS320C64x™, the newest member of the TMS320C6000™ (C6000™) family, is used in high-performance DSP applications. The C64x™ processes information at a rate of 4800 MIPs, while operating at a clock rate of 600 MHz. Processing data at these extre | Doc
• Driver Examples on the DM642 EVM (Rev. A)
The video driver example suite has twelve examples that illustrate the use of the video driver on the DM642 Evaluation Module (EVM). The examples cover all supported video capture- and display formats, and are grouped in seven project categories:NTSC captu | Doc
• TMS320C6000 Enhanced DMA: Example Applications (Rev. A)
The enhanced direct memory access (EDMA) controller is the backbone of the two-level cache architecture for the TMS320C6000? DSPs. The EDMA performs:o cache servicingo host-port servicingo user-programmable data transfers Through proper configuration, EDMA | Doc
• TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D)
Texas Instruments TMS320C6000™ digital signal processors (DSPs) provide a variety of boot configurations that determine which actions are performed after device reset, to prepare for initialization. The boot process is determined by latching the boot con | Doc
• An Audio Example Using Reference Frameworks on the DM642 EVM
The software implements audio examples for Reference Frameworks 3 and Reference Frameworks 5 on the DM642 EVM. These examples are direct ports of the Reference Frameworks examples for the TEB6415 in subdirectories apps/rf3/teb6415 and apps/rf5/projects/teb | Doc
• TMS320C6000 Host Port to MPC860 Interface (Rev. A)
This application report describes an interface between the Motorola MPC860 microprocessor and the host port interface (HPI) of a Texas Instruments TMS320C6000™ (C6000™) digital signal processor (DSP) device. This document includes a schematic showing c | Doc
• JPEG Motion on the DM642 EVM (Rev. A)
This software demonstration combines real−time D1 Joint Photographic Experts Group (JPEG) encoding and decoding of images on the DM642 Evaluation Module (EVM) with networking functionality.The JPEG standard pertains to compression of still images. Perfor | Doc
• Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A)
This document describes how to use the mulit-channel buffered serial ports (McBSP) in the Texas Instruments (TI) TMS320C6000™ digital signal processor (DSP) as a high-speed data communication port.One McBSP of one C6000™ DSP device can be connected to | Doc
• A DSP/BIOS AIC23 Codec Device Driver for the TMS320DM642 EVM
This document describes the usage and design of a device driver for the AIC23 audio codec on the TMS320DM642 EVM. This device driver is written in conformance to the DSP/BIOS™ IOM device driver model and uses the generic TMS320C6x1x EDMA McASP driver to | Doc
• TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A)
This document describes how to interface the multichannel buffered serial port (McBSP) in the TMS320C6000? digital signal processor (DSP) to a voice band audio processor (VBAP). The VBAP under discussion is the TI TLV320AC56, 3V, 2.048 MHz audio processo | Doc
• TMS320DM64x Power Consumption Summary (Rev. F)
This document discusses the power consumption of the Texas Instruments TMS320DM640, TMS320DM641, TMS320DM642, and TMS320DM643 digital signal processors (DSPs). Power consumption on these devices is highly application-dependent, so a spreadsheet is provided | Doc
• JPEG Netcam on the DM642 EVM (Rev. A)
This software demonstration combines real-time D1 Joint Photographic Experts Group (JPEG) encoding and decoding of images on the DM642 Evaluation Module (EVM) with networking functionality.The JPEG standard pertains to compression of still images. Perform | Doc
• TMS320C6000 McBSP: I2S Interface
This document describes how to use the multichannel buffered serial port (McBSP) in the Texas Instruments (TI)(TM) TMS320C6000 digital signal processors (DSP) to interface with devices that conform to the Inter-IC Sound (I2S) specification. I2S is a proto | Doc
• Migrating from TMS320DM642/3/1/0 to the TMS320DM647/DM648 Device
This application report describes issues of interest related to migration from the TMS320DM642/3/1/0 to the TMS320DM648/7 device. The objective of this document is to indicate differences between the two device portfolios. Functions that are identical betw | Doc
• Video Scaling Example on the DM642 EVM
The video scaling example demonstrates the real time video rescaling on DM642 EVM.The input video frames are scaled in different sizes and displayed on a VGA monitor. | Doc
• TMS320C6000 u-Law and a-Law Companding with Software or the McBSP
This document describes how to perform data companding with the TMS320C6000(tm)digital signal processors(DSP). Companding refers to the compression and expansion of transfer data before and after transmission, respectively.The multichannel buffered serial | Doc
• Adapting the SPRA904 Motion Detection Application Report to the DM642 EVM
This application report describes the modifications that needed to be made to the multichannel motion detection system described in application report, A Multichannel Motion Detection System Using eXpressDSP RF5 NVDK Adaptation (literature number SPRA904) | Doc
• High Resolution Video Using the DM642 DSP and the THS8200 Driver (Rev. A)
The DM642 DSP has three 20-bit video ports capable of high definition (HD) display. The video ports can be programmed to follow HDTV standards, such as SMPTE274M and SMPTE296M. These HDTV standards follow a 4:2:2 convention where luminance and chrominance | Doc
• TMS320C6000 McBSP as a TDM Highway (Rev. A)
This document describes how the multichannel buffered serial ports (McBSP) in the TMS320C6000™ digital signal processors (DSP) are used to communicate on a time-division multiplexed (TDM) data highway.TDM provides multiple devices a time slot to perform | Doc
• JPEG Netcam2 on the DM642 EVM (Rev. A)
This software demonstration combines real-time D1 Joint Photographic Experts Group (JPEG) encoding of images on the DM642 Evaluation Module (EVM) with networking functionality.The JPEG standard pertains to compression of still images. Performing JPEG at t | Doc
• TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B)
This document describes how the multichannel buffered serial ports (McBSPs) in the Texas Instruments TMS320C6000™ digital signal processor (DSP) are used to communicate to a single-rate Serial Telecom (ST)-BUS-compliant device.The McBSP receives the fram | Doc
• TMS320C6000 System Clock Circuit Example (Rev. A)
This document describes how to provide the Texas Instruments TMS320C6000™ DSP with a system clock. All of the clocks internal to the C6000™ are generated from a single source through the CLKIN pin. This source clock for the device is an external signal | Doc
• Interfacing an LCD Controller to a DM642 Video Port (Rev. B)
There is an increasing demand to bring video and image processing capabilities to devices like video IP phones, cellular phones, and personal data assistants (PDAs). The images are brought to the user on liquid crystal displays that usually use thin film t | Doc
• Introduction to TMS320C6000 DSP Optimization
The TMS320C6000™ Digital Signal Processors (DSPs) have many architectural advantages that make them ideal for computation-intensive real-time applications. However, to fully leverage the architectural features that C6000™ processors offer, code optimiz | Doc
• Thermal Considerations for the DM64xx, DM64x, and C6000 Devices
As integrated circuit (IC) components become more complex, the challenge of producing an end product with superior thermal performance increases. Thermal performance is a system level concern, impacted by IC packaging as well as by printed circuit board (P | Doc
• The TMS320DM642 Video Port Mini-Driver (Rev. A)
This application report describes the usage and design of the video capture and display mini-drivers that work on the TMS320DM642 Evaluation board (EVM). These device drivers are compliant with the DSP/BIOS™ IOM device driver model. The DSP?s EDMA is use | Doc
• TMS320DM642 to TMS320DM6437 Migration Guide
This document describes device considerations for migrating a design based on a TI TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor (DSP) to one based on a TI TMS320DM6437 Digital Media Processor (DMP). These two devices are based on similar | Doc
• TMS320C6000 Board Design for JTAG (Rev. C)
Designing a TMS320C6000™ DSP board to utilize all of the functionality of the JTAG scan path is a simple process, but a few considerations must be taken into account. The default state of the emulation signals determines whether the JTAG port is used for | Doc
• On-Screen-Display Driver Examples For DM642 EVM Demo Software Release Report
The On-Screen-Display (OSD) driver examples illustrate the usage of the OSD driver on the DM642 EVM. The examples also cover all display formats supported by the OSD FPGA of the DM642 EVM. | Doc
• JPEG Loop Back on the DM642 EVM
The software demonstrates real-time D1 JPEG encoding and decoding of images on a DM642 EVM. The JPEG standard pertains to compression of still images. Performing JPEG at the rate of 30 frames per second, in isolation, as individual images, is considered mo | Doc
• TMS320C6000 McBSP Initialization (Rev. C)
The TMS320C6000? multichannel buffered serial port (McBSP) can operate in a variety of modes, as per application requirements. For proper operation, the serial port must be initialized in a specific order. This document describes the initialization steps n | Doc
• Using a TMS320C6000 McBSP for Data Packing (Rev. A)
This application report describes how to use the multichannel buffered serial port (McBSP) in the Texas Instruments TMS320C6000™ digital signal processor (DSP) for data packing. Data packing involves moving either multiple successive 8-bit elements to/f | Doc
• TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C)
This application report describes an interface between the Texas Instruments TMS320C6000™ DSP host port and the PLX Technology PCI9050 (PCI9052), the PCI interface chip. The PCI9052 is functionally the same as the PCI9050. The only difference between the | Doc
• TMS320DM642 EVM Daughtercard Specification Revision 1.0
The daughtercard specification is based on the interface provided with the TMS320DM642 (DM642) Evaluation Module (EVM). This specification provides the information ecessary to allow daughtercards to be designed to function with the DM642 EVM. It also prov | Doc
Evaluation Kits
TMDSEMU560V2STM-U: XDS560v2 System Trace USB Debug Probe
XDS560TRACE: XDS560 Trace Emulator
TMDSEMU200-U: XDS200 USB Debug Probe
TMDXDMK642: DM64x Digital Media Developer's Kit with NTSC Camera
TMDSEVM642: DM642 Evaluation Module
TMDSEMU560V2STM-UE: XDS560v2 System Trace USB & Ethernet Debug Probe

 

Features, Applications

Features

1024M-Byte Total Addressable External Memory Space Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) 10/100 Mb/s Ethernet MAC (EMAC) IEEE 802.3 Compliant Media Independent Interface (MII) 8 Independent Transmit (TX) Channels and 1 Receive (RX) Channel Management Data Input/Output (MDIO) Three Configurable Video Ports Providing a Glueless I/F to Common Video Decoder and Encoder Devices Supports Multiple Resolutions/Video Stds VCXO Interpolated Control Port (VIC) Supports Audio/Video Synchronization Host-Port Interface (HPI) 32-Bit/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2 Multichannel Audio Serial Port (McASP) Eight Serial Data Pins Wide Variety of I2S and Similar Bit Stream Format Integrated Digital Audio I/F Transmitter Supports S/PDIF, AES-3, CP-430 Formats Inter-Integrated Circuit (I2C BusTM) Two Multichannel Buffered Serial Ports Three 32-Bit General-Purpose Timers Sixteen General-Purpose I/O (GPIO) Pins Flexible PLL Clock Generator IEEE-1149.1 (JTAG) BoundaryScan-Compatible 548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch 548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch 0.13-m/6-Level Cu Metal Process (CMOS) 3.3-V I/O, 1.2-V Internal (-500) 3.3-V I/O, 1.4-V Internal -600, -720)

High-Performance Digital Media Processor 1.67-, 1.39-ns Instruction Cycle Time 600-, 720-MHz Clock Rate Eight 32-Bit Instructions/Cycle MIPS Fully Software-Compatible With C64xTM VelociTI.2TM Extensions to VelociTITM Advanced Very-Long-Instruction-Word (VLIW) TMS320C64xTM DSP Core Eight Highly Independent Functional Units With VelociTI.2TM Extensions: Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle Two Multipliers Support Four x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight x 8-Bit Multiplies (16-Bit Results) per Clock Cycle Load-Store Architecture With Non-Aligned Support 64 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size All Instructions Conditional Instruction Set Features Byte-Addressable (8-/16-/32-/64-Bit Data) 8-Bit Overflow Protection Bit-Field Extract, Set, Clear Normalization, Saturation, Bit-Counting VelociTI.2TM Increased Orthogonality L1/L2 Memory Architecture (16K-Byte) L1P Program Cache (Direct Mapped) (16K-Byte) L1D Data Cache (2-Way Set-Associative) (256K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation) Endianess: Little Endian, Big Endian 64-Bit External Memory Interface (EMIF) Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. Windows is a registered trademark of Microsoft Corporation. I2C Bus is a trademark of Philips Electronics N.V.. All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Description

The TMS320C64xTM DSPs (including the TMS320DM642 device) are the highest-performance fixed-point DSP generation in the TMS320C6000TM DSP platform. The TMS320DM642 (DM642) device is based on the second-generation high-performance, advanced VelociTITM very-long-instruction-word (VLIW) architecture (VelociTI.2TM) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The is a code-compatible member of the C6000TM DSP platform. With performance to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the DM642 device offers cost-effective solutions to high-performance DSP programming challenges. The DM642 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64xTM DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units--two multipliers for a 32-bit result and six arithmetic logic units (ALUs)--with VelociTI.2TM extensions. The VelociTI.2TM extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTITM architecture. The DM642 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2880 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 5760 MMACS. The DM642 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000TM DSP platform devices. The DM642 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache a 128-Kbit direct mapped cache and the Level 1 data cache 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists an 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: three configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO interpolated control port (VIC); one multichannel buffered audio serial port (McASP0); an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals. The DM642 device has three configurable video port peripherals (VP0, VP1, and VP2). These video port peripherals provide a glueless interface to common video decoder and encoder devices. The DM642 video port peripherals support multiple resolutions and video standards (e.g., ITU-BT.656, BT.1120, SMPTE 260M, 274M, and 296M). These three video port peripherals are configurable and can support either video capture and/or video display modes. Each video port consists of two channels A and B with a 5120-byte capture/display buffer that is splittable between the two channels. For more details on the Video Port peripherals, see the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629). The McASP0 port supports one transmit and one receive clock zone, with eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from to 32 time slots. The DM642 has sufficient bandwidth to support all 8 serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format. In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.

McASP0 also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range. The VCXO interpolated control (VIC) port provides digital-to-analog conversion with resolution from to 16-bits. The output of the VIC is a single bit interpolated D/A output.For more details on the VIC port, see the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629). The ethernet media access controller (EMAC) provides an efficient interface between the DM642 DSP core processor and the network. The DM642 EMAC support both 10Base-T and or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The DM642 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception.For more details on the EMAC, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628). The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628). The I2C0 port on the TMS320DM642 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices. The DM642 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.

The DM642 device is a code-compatible member of the C6000TM DSP platform. The C64xTM DSP generation of devices has a diverse and powerful set of peripherals. For more detailed information on the device compatibility and similarities/differences among the DM642 and other C64xTM devices, see the TMS320DM642 Technical Overview (literature number SPRU615).


 

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