|Category||Semiconductors => Processors => Digital Signal Processors => Media Processors => DaVinci Video Processors|
|Part family||TMS320DM6446 DaVinci Digital Media System-on-Chip|
|Description||DaVinci Digital Media System-on-Chip 361-NFBGA 0 to 85|
|Company||Texas Instruments, Inc.|
|Datasheet||Download TMS320DM6446 datasheet
|Pin nb||Package type||Ind std||JEDEC code||Package qty||Carrier||Device mark||Width (mm)||Length (mm)||Thick (mm)||Pitch (mm)|
|361||ZWT||NFBGA||S-PBGA-N||90||JEDEC TRAY (5+1)||TMS320||16||16||.9||.8|
|• 5 VIN solution using DCDC Controllers, a LDO, and a Digitally Prog. Sequencer | Doc|
|• Basic Application Loading over the Serial Interface for the DaVinci TMS320DM644x
This application report describes two related pieces of software that are used together to download an application over the DM644x UART0 serial interface and run it out of the ARM internal memory. The discussion begins with a description of a host applicat | Doc
|• Digital Video Using DaVinci SoC
This application report provides a brief video basics overview. The Texas Instruments (TI) TMS320DM6446/DM6443 DaVinciâ„˘ system-on-chip (SoC) devices are capable of YCbCr or red, green, blue (RGB) digital video output; YCbCr outputs can interface with a v | Doc
|• High-Speed Interface Layout Guidelines (Rev. F) | Doc|
|• Host USB Support on the DVEVM
The TMS320DM6446 device can be configured as a universal serial bus (USB) host or slave device. When configured as a host, it can support USB mass storage devices such as USB flash drives which are widely used today to transfer pictures, music, and documen | Doc
|• EDMA v3.0 (EDMA3) Migration Guide for TMS320DM644x DMSoC
This Document describes migrating from the Texas Instruments TMS320C64x digital signal processor (DSP) enhanced direct memory access (EDMA2) to the TMS320DM644x Digital Media System-on-Chip (DMSoC) EDMA3. This document summarizes the key differences betwee | Doc
|• Understanding the Davinci Preview Engine (Rev. A)
The Preview Engine block in the DaVinci video processing sub-system (VPSS) provides some critical functions for image and video processing. These functions, if implemented in software, require a significant number of computations in terms of million instru | Doc
|• USB Compliance Checklist (Rev. A) | Doc|
|• De-Interlacing and YUV 4:2:2 to 4:2:0 Conversion on DM6446 Using the Resizer (Rev. B)
Video signals captured directly from charge-coupled device (CCD) cameras naturally have interlaced effects and are in a 4:2:2 interleaved format. They typically need to be converted to a 4:2:0 planar format before being encoded because most video compressi | Doc
|• EncodeDecode Demo for the DaVinci DVEVM/DVSDK 1.2 (Rev. A) | Doc|
|• Running Demo via ddd on the DVEVM
The TMS320DM6446 device includes an ARM core which can run the very popular LinuxÂ® operating system. One of Linux strengths is its open source approach enabling developers a wide range of development tools from free open source debugger applications such | Doc
|• Building GStreamer
This Application Report has been contributed to the TI DaVinci & OMAP Developer Wiki. To see the most recently updated version or to contribute, visit this topic at http://wiki.davincidsp.com/index.php?title=GStreamerGStreamer is a pipeline-based multi | Doc
|• Ultrasound Scan Conversion on TI's C64x+ DSPs
One of the recent significant developments in ultrasound is the emergence of portable and handheld ultrasound machines and their rapid acceptance in the market place.Because of their power efficiency and high performance, digital signal processor (DSP) bas | Doc
|• Building a Small Embedded Linux Kernel Example (Rev. A)
Building a Small Embedded Linux Kernel Example Application Report | Doc
|• DaVinci Technology Background and Specifications (Rev. A) | Doc|
|• Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A)
This application report motivates the way the DDR high-speed timing requirements are now going to be communicated to system designers. The traditional method of using data sheet parameters and simulation models is tedious. The system designer uses this inf | Doc
|• TMS320DM6441 Power Consumption Summary Application Report
This document discusses the power consumption of the Texas Instruments TMS320DM6441 digital media System-on-Chip (DMSoC). Power consumption on the DM6441 device is highly application-dependent, so a spreadsheet is provided to model power consumption for a | Doc
|• Encode Demo for the DaVinci DVEVM/DVSDK 1.2 (Rev. A) | Doc|
|• TMS320DM6446 to TMS320DM6467 Migration
This document describes considerations for migration from Texas Instruments TMS320DM6446 Digital Media System-on-Chip (DMSoC) to the TMS320DM6467 DMSoC. Both devices feature a dual-core architecture utilizing a high-performance TMS20C64x+â„˘ Digital Signal | Doc
|• Booting DaVinci EVM from NAND Flash (Rev. A)
Currently, the DaVinciâ„˘ evaluation module (DVEVM) supports three boot modes: the DVEVM can boot from NOR (default), NAND, or universal asynchronous receiver/transmitter (UART). NOR Flash offers the advantages of one-byte random access and execute-in-plac | Doc
|• Running a TMS320C64x+ Codec Across TMS320C64x+ Based DSP Platforms
This application report describes the device differences to be taken care for running the C64x+â„˘ video codec software on different C64x+ based platforms. This document assumes that the codec software is developed for the C64x+ digital signal processor (D | Doc
|• Implementing DDR2 PCB Layout on the TMS320DM644x DMSoC (Rev. G)
This application report contains implementation instructions for the DDR2 interface contained on the TMS320DM644x digital signal processor (DSP) device. The approach to specifying interface timing for the DDR2 interface is quite different than on previous | Doc
|• Measuring Video Quality With the TMS320DM6446 DVSDK
The transmission of video sequences is enabled by compressing the video content with different video encoding algorithms at the source and decoding the stream at the destination. The compression process discards part of the original information and decreas | Doc
|• Creating a TMS320DM6446 Audio Encode Example Using XDC Tools (Rev. A)
This application report describes how to create an eXpressDSPâ„˘ Algorithm for Digital Media (XDM) compatible audio encode example on the TMS320DM6446 processor using the eXpressDSP Components (XDC) tool. XDM is an extension of TI eXpress DSP Algorithm Int | Doc
|• Changing the DVEVM Memory Map
This document describes how to configure Codec Engine-based audio/video applications on the DM6446 (DaVinci) for use in a system that has less than the 256 MB of DDR2 memory that the evaluation board provides. Specifically, we present steps for shrinking m | Doc
|• Fast Development with DaVinci On Screen Display (OSD)
While On Screen Display (OSD) functionality became prevalent as a cheaper alternative to using buttons/knobs to control television settings, in today's society, it seems like everyday a new gadget comes out which uses OSDs.Imagine a video phone or set-top | Doc
|• TMS320DM6446 to TMS320DM6437 Migration Guide
This application report describes device considerations for migrating a design based on a TI TMS320DM6446 Digital Media System-on-Chip (SoC) to one based on a TI TMS320DM6437 Digital Media Processor (DMP). These two devices have many similarities; they bot | Doc
|• Understanding the Davinci Resizer (Rev. B)
The image-scaling operation is one of the most commonly used video and imaging processing functions. The resizer hardware module in the DaVinciâ„˘ video processing subsystem (VPSS) provides the scaling capability in hardware, therefore off-loading the syst | Doc
|• Introduction to TMS320C6000 DSP Optimization
The TMS320C6000â„˘ Digital Signal Processors (DSPs) have many architectural advantages that make them ideal for computation-intensive real-time applications. However, to fully leverage the architectural features that C6000â„˘ processors offer, code optimiz | Doc
|• TMS320DM644x Thermal Considerations (Rev. A) | Doc|
|• DaVinci System Level Benchmarking Measurements
The DaVinciâ„˘ platform offers a complete solution for many multimedia applications requiring advanced video codecs. The solution consists of a DM644x dual core architecture that offers high performance along with a rich mix of peripherals and a complete s | Doc
|• TMS320DM6446/3 Power Consumption Summary (Rev. B)
This document discusses the power consumption of the Texas Instruments TMS320DM6446 and TMS320DM6443 digital media System-on-Chip (DMSoC). Power consumption on the DM6446/3 devices is highly application-dependent, so spreadsheets are provided to model powe | Doc
|• Booting and Flashing via the DaVinci TMS320DM644x Serial Interface (Rev. A)
This application report describes two related pieces of software that are used together to boot the ARM core of the DM644x via the universal asynchronous receiver/transmitter (UART0) serial interface. Additionally, this software allows you to write the nee | Doc
|• EDMA v2.0 to EDMA v3.0 (EDMA3) Migration Guide (Rev. A)
This application report summarizes the key differences between the enhanced direct memory access (EDMA3) used on C64x+â„˘ DSP devices and the EDMA2 used on TMS320C64xâ„˘ DSP devices, and provides guidance for migrating from EDMA2 to EDMA3. | Doc
|• Compact Flash (CF) Support on the DVEVM
The TMS320DM6446 device has a rich set of peripherals; however, many of these peripherals are multiplexed with each other, and only one is available at a time.Perhaps the best example of a multiplexing scenario found on the TMS320DM6446 device is the async | Doc
|• Decode Demo for the DaVinci DVEVM/DVSDK 1.2 (Rev. A) | Doc|
|• Common Object File Format (COFF) | Doc|
|• Motion JPEG Demo on TMS320DM6446 (Rev. A)
This application report describes how to build a motion JPEG demo running on Texas Instruments DM6446 processor leveraging the JPEG codec combo and XDC tools provided with the DM6446 DVEVM/DVSDK package. The demo is derived from the motion JPEG demo runnin | Doc
|• TMS320DM6446 594 MHz to 810 MHz Migration Guide
This application report is intended to provide an overview of changes necessary to upgrade a DM6446-based design from the 513 MHz or 594 MHz device to an 810 MHz device. The changes listed below are required by the 810 MHz device for proper operation; othe | Doc
|• Using Static IP Between Linux Host and the DVEVM
The typical development environment for the TMS320DM644x EVM devices, also known as the digital video evaluation module (DVEVM), involves connecting a host workstation to the target EVM. This environment allows for the bulk of the development to be done in | Doc
|• TMS320C64x to TMS320C64x+ CPU Migration Guide (Rev. A)
This document describes migration from the Texas Instruments TMS320C64xâ„˘ digital signal processor (DSP) to the TMS320C64x+â„˘ DSP. The objective of this document is to indicate differences between the two cores and to briefly describe new features. Funct | Doc
|• LSP 2.10 DaVinci Linux Drivers (Rev. A) | Doc|
|• TMS320DM644x ROM Migration Guide
This application report describes ROM bootloader (RBL) differences between silicon revision 2.1 and 2.3 of the TMS320DM644x Digital Media System-on-Chip (DMSoC). | Doc
|TMDSEMU560V2STM-U: XDS560v2 System Trace USB Debug Probe|
|TMDSADP: Adaptive Clocking JTAG Emulator Adapters|
|TMDSEMU200-U: XDS200 USB Debug Probe|
|TMDSEMU560V2STM-UE: XDS560v2 System Trace USB & Ethernet Debug Probe|
ARM926EJ-S (MPU) Core Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets DSP Instruction Extensions and Single Cycle MAC ARM® Jazelle® Technology EmbeddedICE-RTTM Logic for Real-Time Debug ARM9 Memory Architecture 16K-Byte Instruction Cache 8K-Byte Data Cache 16K-Byte RAM 16K-Byte ROM Embedded Trace BufferTM (ETB11TM) With 4KB Memory for ARM9 Debug Endianness: Little Endian for ARM and DSP Video Processing Subsystem Front End Provides: CCD and CMOS Imager Interface BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface Preview Engine for Real-Time Image Processing Glueless Interface to Common Video Decoders Histogram Module Auto-Exposure, Auto-White Balance and Auto-Focus Module Resize Engine Resize Images From to 4x Separate Horizontal/Vertical Control Back End Provides: Hardware On-Screen Display (OSD) Four 54-MHz DACs for a Combination of Composite NTSC/PAL Video Luma/Chroma Separate Video (S-video) Component (YPbPr or RGB) Video (Progressive) Digital Output 8-/16-bit YUV to 24-Bit RGB HD Resolution to 2 Video Windows
High-Performance Digital Media SoC 594-MHz C64x+TM Clock Rate 297-MHz ARM926EJ-STM Clock Rate Eight 32-Bit C64x+ Instructions/Cycle 4752 C64x+ MIPS Fully Software-Compatible With / ARM9TM Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+TM DSP Core Eight Highly Independent Functional Units Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle Two Multipliers Support Four x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight x 8-Bit Multiplies (16-Bit Results) per Clock Cycle Load-Store Architecture With Non-Aligned Support 64 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size All Instructions Conditional Additional C64x+TM Enhancements Protected Mode Operation Exceptions Support for Error Detection and Program Redirection Hardware Support for Modulo Loop Operation C64x+ Instruction Set Features Byte-Addressable (8-/16-/32-/64-Bit Data) 8-Bit Overflow Protection Bit-Field Extract, Set, Clear Normalization, Saturation, Bit-Counting Compact 16-Bit Instructions Additional Instructions to Support Complex Multiplies C64x+ L1/L2 Memory Architecture 32K-Byte L1P Program RAM/Cache (Direct Mapped) 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative) 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. C6000, I2C bus, I2C-bus are trademarks of Texas Instruments. All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
External Memory Interfaces (EMIFs) 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O) Asynchronous16-Bit Wide EMIF (EMIFA) With 128M-Byte Address Reach Flash Memory Interfaces NOR (8-/16-Bit-Wide Data) NAND (8-/16-Bit-Wide Data) Flash Card Interfaces Multimedia Card (MMC)/Secure Digital (SD) CompactFlash Controller With True IDE Mode SmartMedia Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers) One 64-Bit Watch Dog Timer Three UARTs (One with RTS and CTS Flow Control) One Serial Port Interface (SPI) With Two Chip-Selects Master/Slave Inter-Integrated Circuit (I2C BusTM) Audio Serial Port (ASP) AC97 Audio Codec Interface Standard Voice Codec Interface (AIC12)
10/100 Mb/s Ethernet MAC (EMAC) IEEE 802.3 Compliant Media Independent Interface (MII) VLYNQTM Interface (FPGA Interface) USB Port With Integrated 2.0 PHY USB 2.0 High-/Full-Speed (480-Mbps) Client USB 2.0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device) Three Pulse Width Modulator (PWM) Outputs On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART ATA/ATAPI I/F (ATA/ATAPI-5 Specification) Individual Power-Saving Modes for ARM/DSP Flexible PLL Clock Generators IEEE-1149.1 (JTAG) BoundaryScan-Compatible to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions) 361-Pin Pb-Free BGA Package (ZWT Suffix), 0.8-mm Ball Pitch 0.09-µm/6-Level Cu Metal Process (CMOS) 3.3-V and 1.8-V I/O, 1.2-V Internal Applications: Digital Media Networked Media Encode/Decode Video ImagingDescription
The TMS320DM6446 (also referenced as DM6446) leverages TI's Davinci technology to meet the networked media encode and decode application processing needs of next-generation embedded devices. The DM6446 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture of the DM6446 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+ DSP core and an ARM926EJ-S MPU core. The a 32-bit RISC processor core that performs or 16-bit instructions and processes or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core incorporates: A coprocessor 15 (CP15) and protection module Data and program Memory Management Units (MMUs) with table look-aside buffers. Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The TMS320C64x+TM DSPs are the highest-performance fixed-point DSP generation in the
TMS320C6000TM DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSP cores an excellent choice for digital media applications. The is a code-compatible member of the C6000TM DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+ DSP with added functionality and an expanded instruction set. Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively. With performance to 4752 million instructions per second (MIPS) at a clock rate of 594 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units--two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2376 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4752 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732). The DM6446 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6446 core uses a two-level cache-based architecture. The Level 1 program cache a 256K-bit direct mapped cache and the Level 1 data cache 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: 2 configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; 71-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2. The DM6446 device includes a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals: 1 Video Processing Front-End (VPFE) input used for video capture, 1 Video Processing Back-End (VPBE) output with imaging co-processor (VICP) used for display. The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV422. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM6446. The Resizer accepts image data for separate horizontal and vertical resizing from 4x in increments of 256/N, where N is between 64 and 1024. The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides to 24 bits of digital output to interface to RGB888 devices. The digital output is capable 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.
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TMS320VC5402AGGU16 : TMS320 Family. ti TMS320VC5402A, Fixed-point Digital Signal Processor.
TMS320VC5509A : Fixed-point Digital Signal Processorthe TMS320VC5509A Fixed-point Digital Signal Processor (DSP) is Based on The TMS320C55x DSP Generation Cpu Processor Core. The C55x DSP Architecture Achieves High Performance And Low Power Through Increased Parallelism And Total Focus on Reduction in Power Dissipation. The Cpu Supports an Internal Bus Structure That.
Z86C95 : CMOS z8 Digital Signal Processor ( DSP ). The Z86C95 MCU (Microcontroller Unit ) introduces a new level of sophistication to SuperintegrationTM ICs. The is a member of the Z8® single-chip microcontroller family incorporating a CMOS ROMless Z8 microcontroller with an embedded DSP processor for digital servo control. The DSP slave processor can perform x 16-bit multiplicates and accumulates in one clock.
MC56F8023PB : The 56F8023 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs). It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program.
MSC8154 : Quad-Core Digital Signal Processor • Four StarCore SC3850 DSP subsystems, each with an SC3850 DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, unified 512 Kbyte L2 cache configurable as M2 memory in 64 Kbyte increments, memory management unit (MMU), extended programmable interrupt controller (EPIC), two general-purpose 32-bit timers,.
TMX320C6655CZH : Fixed And Floating Point Digital Signal Processor The TMS320C6657/55 Multicore Fixed and Floating Point Digital Signal Processors are based on TI\'s KeyStone multicore architecture. The C6657 is integrated with two C66x DSP CorePacs running at 0.85, 1.0 or 1.25 GHz. The C6655 contains one C66x DSP CorePac running at 1.0 or 1.25 GHz. These devices support.