|Category||Semiconductors => Processors => Other Processors|
|Part family||TMS320F206 Digital Signal Processor|
|Title||TMS320 Family->TMS320C20X Family|
|Description||Digital Signal Processor 100-LQFP 0 to 70|
|Company||Texas Instruments, Inc.|
|Datasheet||Download TMS320F206PZ datasheet
|Pin nb||Package type||Ind std||JEDEC code||Package qty||Carrier||Device mark||Width (mm)||Length (mm)||Thick (mm)||Pitch (mm)|
|• Using Triple Read and Boost Algorithm Code to Enhance Adequate Prog Margin
This addendum to the TMS320F20x/F24x DSP Embedded Flash Memory Technical Reference (SPRU282) describes the triple read and boost operation of the embedded Flash EEPROM module on the TMS320F20x digital signal processor (DSP) devices to enhance the programmi | Doc
High-Performance Static CMOS Technology Includes the T320C2xLP Core CPU is a Member of the TMS320C20x Generation, Which Also Includes the TMS320C203, and TMS320C209 Devices Instruction-Cycle Time 5 V Source Code Compatible With TMS320C25 Upwardly Code-Compatible With TMS320C5x Devices Three External Interrupts TMS320F206 Integrated Memory: Words of On-Chip Dual-Access Data RAM × 16 Words of On-Chip Flash Memory (EEPROM) × 16 Words of On-Chip Single-Access Program/ Data RAM × 16-Bit Maximum Addressable External Memory Space 64K Program 64K Data 64K Input/Output (I/O) 32K Global
32-Bit ALU / Accumulator × 16-Bit Multiplier With a 32-Bit Product Block Moves from Data and Program Space TMS320F206 Peripherals: On-Chip 16-Bit Timer On-Chip Software-Programmable Wait-State to 7) Generator On-Chip Oscillator On-Chip Phase-Locked Loop (PLL) Six General-Purpose I/O Pins Full-Duplex Asynchronous Serial Port (UART) Enhanced Synchronous Serial Port (ESSP) With Four-Level-Deep FIFOs Input Clock Options Options Multiply-by-One, -Two, or -Four and Divide-by-Two Support of Hardware Wait States Power Down IDLE Mode IEEE 1149.1-Compatible Scan-Based Emulation 100-Pin Thin Quad Flat Package (TQFP) (PZ Suffix)description
The TMS320F206 Texas Instruments (TITM) digital signal processor (DSP) is fabricated with static CMOS integrated-circuit technology, and the architectural design is based upon that of the TMS320C20x series, optimized for low-power operation. The combination of advanced Harvard architecture, on-chip peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational flexibility and speed of the 'F206. The 'F206 offers these advantages:
32K 16 words on-chip flash EEPROM reduces system cost and facilitates prototyping Enhanced TMS320 architectural design for increased performance and versatility Advanced integrated-circuit processing technology for increased performance 'F206 devices are pin- and code-compatible with 'C203 devices. Source code for the 'F206 DSP is software-compatible with the 'C1x and 'C2x DSPs and is upwardly compatible with fifth-generation DSPs ('C5x) New static-design techniques for minimizing power consumption and increasing radiation tolerance
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. is a trademark of Texas Instruments Incorporated. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Table 1 shows the capacity of on-chip RAM and ROM, the number of serial and parallel I/O ports, the execution time of one machine cycle, and the type of package with total pin count of the TMS320F206 device. Table 1. Characteristics of the TMS320F206 Processor
ON-CHIP MEMORY DEVICE DATA TMS320F206 288 RAM DATA/ PROG + 256 ROM PROG FLASH EEPROM PROG 32K I/O PORTS POWER SUPPLY (V) 5 CYCLE TIME (ns) 50 PACKAGE TYPE WITH PIN COUNT 100-pin TQFP
TERMINAL NAME NO. A1 A0 TYPE DESCRIPTION DATA AND ADDRESS BUSES Parallel data bus D15 [most significant bit (MSB)] through D0 [least significant bit (LSB)]. D15D0 are used to transfer data between the TMS320F206 and external data / program memory / O devices. Placed in the high-impedance state when not outputting / W high) or RS when asserted. They go into the high-impedance state when OFF is active low.
Parallel address bus A15 (MSB) through A0 (LSB). A15A0 are used to address external data / program memory / O devices. These signals go into the high-impedance state when OFF is active low.
MEMORY CONTROL SIGNALS 51 52 O/Z Program-select signal. PS is always high unless low-level asserted for communicating to off-chip program space. PS goes into the high-impedance state when OFF is active low. Data-select signal. DS is always high unless low-level asserted for communicating to off-chip program space. DS goes into the high-impedance state when OFF is active low. / O space-select signal. IS is always high unless low-level asserted for communicating to I/O ports. IS goes into the high-impedance state when OFF is active low. Data-ready input. READY indicates that an external device is prepared for the bus transaction to be completed. If the external device is not ready (READY low), the TMS320F206 waits one cycle and checks READY again. If READY is not used, it should be pulled high. Read / write signal. / W indicates transfer direction when communicating with an external device. R/W is normally in read mode (high), unless low level is asserted for performing a write operation. / W goes into the high-impedance state when OFF is active low. Read-select indicates an active, external read cycle. RD is active on all external program, data, and / O reads. RD goes into the high-impedance state when OFF is active low. The function of the RD pin can be programmed to provide an inverted R/W signal instead of RD. The FRDN bit (bit 15) in the PMST register controls this selection.I = input, O = output, Z = high impedance, PWR = power, GND = ground
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