|Description||5 Volt, Byte Alterable E2PROM|
|Datasheet||Download X28C256DM-20 datasheet
The 8 E2PROM, fabricated with Xicor's proprietary, high performance, floating gate CMOS technology. Like all Xicor programmable nonvolatile memories the a 5V only device. The X28C256 features the JEDEC approved pinout for bytewide memories, compatible with industry standard RAMs. The X28C256 supports a 64-byte page write operation, effectively providing a 78µs/byte write cycle and enabling the entire memory to be typically written in less than 2.5 seconds. The X28C256 also features DATA and Toggle Bit Polling, a system software support scheme used to indicate the early completion of a write cycle. In addition, the X28C256 includes a user-optional software data protection mode that further enhances Xicor's hardware write protect capability. Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years.
Access Time: 200ns Simple Byte and Page Write Single 5V Supply --No External High Voltages or VPP Control Circuits Self-Timed --No Erase Before Write --No Complex Programming Algorithms --No Overerase Problem Low Power CMOS: --Active: 60mA --Standby: 200µA Software Data Protection Protects Data Against System Level Inadvertent Writes High Speed Page Write Capability Highly Reliable Direct WriteTM Cell Endurance: 100,000 Write Cycles Data Retention: 100 Years Early End of Write Detection DATA Polling --Toggle Bit Polling
PIN DESCRIPTIONS Addresses (A0A14) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations. Data In/Data Out (I/O0I/O7) Data is written to or read from the X28C256 through the I/O pins. Write Enable (WE) The Write Enable input controls the writing of data to the X28C256. PIN CONFIGURATION
PIN NAMES Symbol CE OE VCC VSS NC Description Address Inputs Data Input/Output Write Enable Chip Enable Output Enable +5V Ground No ConnectX BUFFERS LATCHES AND DECODER A0A14 ADDRESS INPUTS Y BUFFERS LATCHES AND DECODER
DEVICE OPERATION Read operations are initiated by both OE and CE LOW. The read operation is terminated by either or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will in a high impedance state when either CE is HIGH. Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28C256 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms. Page Write Operation The page write feature of the X28C256 allows the entire memory to be written in 2.5 seconds. Page write allows two to sixty-four bytes of data to be consecutively written to the X28C256 prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A6 through A14) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to sixty-three bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100µs of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100µs, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100µs. Write Operation Status Bits The X28C256 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1. Figure 1. Status Bit Assignment
DATA Polling (I/O7) The X28C256 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28C256, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e. write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data. Note: If the is in the protected state and an illegal write operation is attempted DATA Polling will not operate. Toggle Bit (I/O6) The X28C256 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle I/O6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations.
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