Details, datasheet, quote on part number: X28C512
CategoryMemory => ROM => EEPROM => Parallel
Description512K Bit CMOS EePROM (64K X 8)
CompanyXicor, Inc.
DatasheetDownload X28C512 datasheet
Find where to buy


Features, Applications


Access Time: 90ns Simple Byte and Page Write --Single 5V Supply No External High Voltages or VPP Control Circuits --Self-Timed --No Erase Before Write --No Complex Programming Algorithms --No Overerase Problem Low Power CMOS: --Active: 50mA --Standby: 500A Software Data Protection --Protects Data Against System Level Inadvertant Writes High Speed Page Write Capability Highly Reliable Direct WriteTM Cell --Endurance: 100,000 Write Cycles --Data Retention: 100 Years Early End of Write Detection --DATA Polling --Toggle Bit Polling

Two PLCC and LCC Pinouts --X28C010 E2PROM Pin Compatible --X28C513 --Compatible with Lower Density E2PROMs


The 8 E2PROM, fabricated with Xicor's proprietary, high performance, floating gate CMOS technology. Like all Xicor programmable nonvolatile memories the a 5V only device. The X28C512/513 features the JEDEC approved pinout for bytewide memories, compatible with industry standard EPROMS. The X28C512/513 supports a 128-byte page write operation, effectively providing a 39s/byte write cycle and enabling the entire memory to be written in less than 2.5 seconds. The X28C512/513 also features DATA Polling and Toggle Bit Polling, system software support schemes used to indicate the early completion of a write cycle. In addition, the X28C512/513 supports the Software Data Protection option.

PIN DESCRIPTIONS Addresses (A0A15) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations. Data In/Data Out (I/O0I/O7) Data is written to or read from the X28C512/513 through the I/O pins. Write Enable (WE) The Write Enable input controls the writing of data to the X28C512/513. PIN NAMES Symbol CE OE VCC VSS NC Description Address Inputs Data Input/Output Write Enable Chip Enable Output Enable +5V Ground No Connect

DEVICE OPERATION Read operations are initiated by both OE and CE LOW. The read operation is terminated by either or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will in a high impedance state when either CE is HIGH. Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28C512/513 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms. Page Write Operation The page write feature of the X28C512/513 allows the entire memory to be written in 2.5 seconds. Page write allows two to one hundred twenty-eight bytes of data to be consecutively written to the X28C512/513 prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A7 through A15) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to one hundred twentyseven bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100s of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100s, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100s. Write Operation Status Bits The X28C512/513 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1. Figure 1. Status Bit Assignment

DATA Polling (I/O7) The X28C512/513 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28C512/ 513, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e. write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data. Toggle Bit (I/O6) The X28C512/513 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle, I/O6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations.


Related products with the same datasheet
Some Part number from the same manufacture Xicor, Inc.
X28C512-12 512K Bit CMOS EePROM (64K X 8)
Same catergory

AT28C010 : 1 Megabit (128k X 8) Paged CMOS E2PROM. Fast Read Access Time 120 ns Automatic Page Write Operation Internal Address and Data Latches for 128-Bytes Internal Control Timer Fast Write Cycle Time Page Write Cycle Time 10 ms Maximum to 128-Byte Page Write Operation Low Power Dissipation 40 mA Active Current 200 A CMOS Standby Current Hardware and Software Data Protection DATA Polling for End of Write.

GS816019 : Sychronous Burst. Pin 14 Note: The s cited in the base datasheet for the products addressed by this errata remain in force except where superseded by the information in this errata. 1/5 s cited are subject to change without notice. For latest documentation see 2/5 s cited are subject to change without notice. For latest documentation see

HYMD116G7258 : 128 MB. 16Mx72 Registered DDR Sdram Dimm. Hynix HYMD116G7258-H/L series is registered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 16Mx72 high-speed memory arrays. Hynix HYMD116G7258-H/L series consists of nine 16Mx8 DDR SDRAM in 400mil TSOP II packages a 184pin glass-epoxy substrate. Hynix HYMD116G7258-H/L series provide a high performance.

HYMD116G725BL8M : 128 MB. 16Mx72 Bits Low Profile Registered DDR Sdram Dimm. Hynix HYMD116G725B(L)8M-M/K/H/L series is low profile registered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 16Mx72 high-speed memory arrays. Hynix HYMD116G725B(L)8M-M/K/H/L series consists of nine 16Mx8 DDR SDRAM in 400mil TSOP II packages a 184pin glass-epoxy substrate. Hynix HYMD116G725B(L)8M-M/K/H/L.

IDT72V293 : 3.3 Volt High-density Supersync Ii(tm) Narrow Bus Fifo. 3.3 VOLT HIGH-DENSITY SUPERSYNC IITM NARROW BUS FIFO x 9 Choose among the following memory organizations: x 9 Functionally compatible with the IDT72V255LA/72V265LA and IDT72V275/72V285 SuperSync FIFOs 133 MHz operation 7.5 ns read/write cycle time (5.0 ns access time) User selectable input and output port bus-sizing to x9 out to x18 out to x9 out to x18 out Big-Endian/Little-Endian.

KM732V688T : SB & SPB. = KM732V688T 64Kx32-Bit Synchronous Pipelined Burst SRAM ;; Organization = 64Kx32 ;; Operating Mode = SPB ;; VDD(V) = 3.3 ;; Access Time-tCD(ns) = 7.0,7.0 ;; Speed-tcyc (MHz) = 75,75 ;; I/o Voltage(V) = 3.3 ;; Package = 100TQFP,100QFP ;; Production Status = Eol ;; Comments = Design is Not Recommended.

KM736V987H : SB & SPB. = KM736V987H 512Kx36 & 1Mx18 Synchronous Burst SRAM ;; Organization = 512Kx36 ;; Operating Mode = SB ;; VDD(V) = 3.3 ;; Access Time-tCD(ns) = 8.5,9.0 ;; Speed-tcyc (MHz) = 100,83 ;; I/o Voltage(V) = 2.5,3.3 ;; Package = 100TQFP,119BGA ;; Production Status = Eol ;; Comments = -.

LHF04C01 : 4m Flash File Memory.

M368L1714DT1 : = M368L1714DT1 16Mx64 DDR Sdram 184pin Dimm Based on 8Mx16 ;; Density(MB) = 128 ;; Organization = 16Mx64 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 4K/64ms ;; Speed = B3,A2,B0,A0 ;; #of Pin = 184 ;; Power = C,l ;; Component Composition = (8Mx16)x8 ;; Production Status = Eol ;; Comments = -.


MX23C8100 : 8M, 1Mx8/512Kx16 100ns. Bit organization x 8 (byte mode) x 16 (word mode) Fast access time - Random access: 100ns (max.) Current - Operating: 60mA - Standby: 50uA Supply voltage - 5V10% Package - 44 pin SOP - 42 pin PDIP - 48 pin TSOP x 12mm) Part No. Access Time MX23C8100TC-15 150ns Package 42 pin PDIP 42 pin PDIP 42 pin PDIP 44 pin SOP 44 pin SOP 44 pin SOP 48 pin TSOP.

U632HM1024 : 1 Mb. Powerstore 128k X 8 Nvsram.

HY5DU281622ALT-K : 8M X 16 DDR DRAM, 0.75 ns, PDSO66. s: Memory Category: DRAM Chip ; Density: 134218 kbits ; Number of Words: 8000 k ; Bits per Word: 16 bits ; Package Type: TSOP, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 ; Pins: 66 ; Logic Family: CMOS ; Supply Voltage: 2.5V ; Access Time: 0.7500 ns ; Operating Temperature: 0 to 70 C (32 to 158 F).

MT9JDF51272AZ-1G4E1 : 4G X 72 DDR DRAM MODULE, DMA240. s: Memory Category: DRAM Chip ; Density: 309237645 kbits ; Number of Words: 4000000 k ; Bits per Word: 72 bits ; Package Type: HALOGENFREE, MO-269, UDIMM-240 ; Pins: 240 ; Logic Family: CMOS ; Supply Voltage: 1.35 ; Operating Temperature: 0 to 70 C (32 to 158 F).

W24257C-10L : 32K X 8 STANDARD SRAM, 100 ns, PDIP28. s: Memory Category: SRAM Chip ; Density: 262 kbits ; Number of Words: 32 k ; Bits per Word: 8 bits ; Package Type: DIP, 0.600 INCH, PLASTIC, DIP-28 ; Pins: 28 ; Logic Family: CMOS ; Supply Voltage: 5V ; Access Time: 100 ns ; Operating Temperature: 0 to 70 C (32 to 158 F).

0-C     D-L     M-R     S-Z