|Category||Communication => Telephony => DTMF (Dual Tone Multiple Frequency) => DTMF Receivers|
|Description||Description = ;; Package Type = SOIC(N) ;; No. Of Pins =|
|Datasheet||Download ZL49031DCA datasheet
Wide dynamic range (50dB) DTMF Receiver Call progress (CP) detection via cadence indication 4-bit synchronous serial data output Software controlled guard time for ZL490x0 Internal guard time circuitry for ZL490x1 Powerdown option ZL4903x) 3.579MHz crystal or ceramic resonator (ZL4903x and ZL4902x) External clock input (ZL4901x) Guarantees non-detection of spurious tones Ordering Information ZL49031DDB 8 Pin PDIP 8 Pin PDIP 8 Pin PDIP 8 Pin PDIP 18 Pin SOIC 18 Pin SOIC 20 Pin SSOP 20 Pin SSOP 18 Pin SOIC 18 Pin SOIC 20 Pin SSOP 20 Pin SSOP Tubes Tape & Tubes Tape & Tubes Tape & Tubes Tape &Applications
Integrated telephone answering machine End-to-end signalling Fax Machines
+85° C signal and requires external software guard time to validate the DTMF digit. The ZL490x1, with preset internal guard times, uses a delay steering (DStD) logic output to indicate the detection of a valid DTMF digit. The 4-bit DTMF binary digit can be clocked out synchronously at the serial data (SD) output. The SD pin is multiplexed with call progress detector output. In the presence of supervisory tones, the call progressDescription
The is a family of high performance DTMF receivers which decode all 16 tone pairs into a 4-bit binary code. These devices incorporate an AGC for wide dynamic range and are suitable for end-to-end signalling. The ZL490x0 provides an early steering (ESt) logic output to indicate the detection of a DTMF
Steering Circuit High Group Filter Antialias Filter Dial Tone Filter Low Group Filter Digital Detector Algorithm Code Converter and LatchDigital Guard Time3 Parallel to Serial Converter & Latch
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
detector circuit indicates the cadence (i.e., envelope) of the tone burst. The cadence information can then be processed by an external microcontroller to identify specific call progress signals. The ZL4902x and ZL4903x can be used with a crystal or a ceramic resonator without additional components. A power-down option is provided for the ZL4901x and ZL4903x.
Pin 1 3 Name INPUT OSC2 OSC1 (CLK) Description DTMF/CP Input. Input signal must be AC coupled via capacitor. Oscillator Output. Oscillator/Clock Input. This pin can either be driven by: 1) an external digital clock with defined input logic levels. OSC2 should be left open. 2) connecting a crystal or ceramic resonator between OSC1 and OSC2 pins. Ground. (0V) Serial Data/Call Progress Output. This pin serves the dual function of being the serial data output when clock pulses are applied after validation of DTMF signal, and also indicates the cadence of call progress input. As DTMF signal lies in the same frequency band as call progress signal, this pin may toggle for DTMF input. The SD pin is at logic low in powerdown state. Acknowledge Pulse Input. After ESt or DStD is high, applying a sequence of four pulses on this pin will then shift out four bits on the SD pin, representing the decoded DTMF digit. The rising edge of the first clock is used to latch the 4-bit data prior to shifting. This pin is pulled down internally. The idle state of the ACK signal should be low. Early Steering Output. A logic high on ESt indicates that a DTMF signal is present. ESt is at logic low in powerdown state. Delayed Steering Output. A logic high on DStD indicates that a valid DTMF digit has been detected. DStD is at logic low in powerdown state.
Positive Power Supply (5V Typ.) Performance of the device can be optimized by minimizing noise on the supply rails. Decoupling capacitors across VDD and VSS are therefore recommended. No Connection. Pin is unconnected internally.
Power Down Input. A logic high on this pin will power down the device to reduce power consumption. This pin is pulled down internally and can be left open if not used. ACK pin should be at logic '0' to power down device.
The ZL490xxs are high performance and low power consumption DTMF receivers. These devices provide wide dynamic range DTMF detection and a serial decoded data output. These devices also incorporate an energy detection circuit. An input voiceband signal is applied to the devices via a series decoupling capacitor. Following the unity gain buffering, the signal enters the AGC circuit followed by an anti-aliasing filter. The bandlimited output is routed to a dial tone filter stage and to the input of the energy detection circuit. A bandsplit filter is then used to separate the input DTMF signal into high and low group tones. The high group and low group tones are then verified and decoded by the internal frequency counting and DTMF detection circuitry. Following the detection stage, the valid DTMF digit is translated a 4-bit binary code (via an internal look-up ROM). Data bits can then be shifted out serially by applying external clock pulses. Automatic Gain Control (AGC) Circuit As the device operates on a single power supply, the input signal is biased internally at approximately VDD/2. With large input signal amplitude (between 0 and approximately -30dBm for each tone of the composite signal), the AGC is activated to prevent the input signal from being clipped. At low input level, the AGC remains inactive and the input signal is passed directly to the hardware DTMF detection algorithm and to the energy detection circuit. Filter and Decoder Section The signal entering the DTMF detection circuitry is filtered by a notch filter at 350 and 440 Hz for dial tone rejection. The composite dual-tone signal is further split into its individual high and low frequency components by two 6th order switched capacitor bandpass filters. The high group and low group tones are then smoothed by separate
|Related products with the same datasheet|
|Some Part number from the same manufacture Zarlink Semiconductor|
|ZL49031DCB Description = ;; Package Type = SOIC(N) ;; No. Of Pins =|
|ZL50010 Description = Flexible 512 Channel TDM Digital Switch With Enhanced DPLL ;; Package Type = LQFP ;; No. Of Pins = 160|
|ZL50011 Description = Flexible 512 Channel TDM Digital Switch With DPLL ;; Package Type = LQFP ;; No. Of Pins = 160|
|ZL50012 Description = Flexible 512 Channel TDM Digital Switch ;; Package Type = LQFP ;; No. Of Pins = 160|
|ZL50015 Enhanced 1 K Channel TDM Switch With Stratum 4E DPLL|
|ZL50016 Enhanced 1 K Channel TDM Switch With Rate Conversion|
|ZL50017 1024 X 1024 Channels Selectable Rate (2, 4, 8 Mbps) Non-blocking TDM Switch|
|ZL50018 Enhanced 2 K Channel TDM Switch With Stratum 3 DPLL|
|ZL50019 Enhanced 2 K Channel TDM Switch With Stratum 4E DPLL|
|ZL50020 Enhanced 2 K Channel TDM Switch With Rate Conversion|
|ZL50021 Enhanced 4 K Channel TDM Switch With Stratum 3 DPLL|
|ZL50022 Enhanced 4 K Channel TDM Switch With Stratum 4E DPLL|
|ZL50023 Enhanced 4 K Channel TDM Switch With Rate Conversion|
|ZL50030 Flexible 4 K X 2 K Channel Digital Switch With H.110 Interface, 32 Bi-directional Backplane Streams And 16 Bi-directional Local Streams|
|ZL50050 8 K Channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16 or 32 Mbps), 32 Input And 32 Output ...|
|ZL50050GAC Description = ;; Package Type = Bga ;; No. Of Pins = 196|
|ZL50051 8 K Channel Digital Switch With High Jitter Tolerance, Single Rate (8 or 16 Mbps) And 64 Input And 64 Output Streams|
|ZL50052 8 K Channel Digital Switch With High Jitter Tolerance, Single Rate (32 Mbps) And 16 Input And 16 Output Streams|
|ZL50053 8 K Channel Digital Switch With High Jitter Tolerance, Single Rate (8 or 16 Mbps) And 64 Input And 64 Output Streams|
|ZL50057 12 K Channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16 or 32 Mbps), 48 Input And 48 Output ...|
|ZL50057GAC Description = ;; Package Type = Bga ;; No. Of Pins = 272|