Details, datasheet, quote on part number: ZL50011/QCC
DescriptionFlexible 512 Channel DX with On-chip DPLL
CompanyZarlink Semiconductor
DatasheetDownload ZL50011/QCC datasheet
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Features, Applications

512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation Rate conversion between the ST-BUS inputs and ST-BUS outputs Integrated Digital Phase-Locked Loop (DPLL) meets Telcordia GR-1244-CORE Stratum 4 specifications DPLL provides reference monitor, jitter attenuation and free run functions Per-stream ST-BUS input with data rate selection of 2.048 Mbps, 4.096 Mbps or 8.192 Mbps Per-stream ST-BUS output with data rate selection of 2.048 Mbps, 4.096 Mbps or 8.192 Mbps; the output data rate can be different than the input data rate Per-stream high impedance control output for every ST-BUS output with fractional bit advancement Per-stream input channel and input bit delay programming with fractional bit delay

Ordering Information 160 Pin LQFP Trays 144 Ball LBGA Trays 160 Pin LQFP* Trays, Bake & Drypack 144 Ball LBGA** Trays, Bake & Drypack *Pb Free Matte Tin Pb Free Tin/Silver/Copper C

Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay Per-channel high impedance output control Per-channel message mode Per-channel Pseudo Random Bit Sequence (PRBS) pattern generation and bit error detection Control interface compatible to Motorola nonmultiplexed CPUs Connection memory block programming capability IEEE-1149.1 (JTAG) test port 3.3 V I/O with 5 V tolerant input

Input Timing Connection Memory Output HiZ Control STOHZ0-15

Figure - ZL50011 Functional Block Diagram Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912, France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08 1

Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.


Small and medium digital switching platforms Access Servers Time Division Multiplexers Computer Telephony Integration Digital Loop Carriers


The device has 16 ST-BUS inputs (STi0-15) and 16 ST-BUS outputs is a non-blocking digital switch with 512 64 kbps channels and performs rate conversion between the ST-BUS inputs and ST-BUS outputs. The ST-BUS inputs accept serial input data streams with the data rate of 2.048 Mbps, 4.096 Mbps or 8.192 Mbps on a per-stream basis. The ST-BUS outputs deliver serial output data streams with the data rate of 2.048 Mbps, 4.096 Mbps or 8.192 Mbps on a per-stream basis. The device also provides 16 high impedance control outputs (STOHZ 0-15) to support the use of external high impedance control buffers. The ZL50011 has features that are programmable on a per-stream or per-channel basis including message mode, input bit delay, output bit advancement, constant throughput delay and high impedance output control. The on-chip DPLL meets Telcordia GR-1244-CORE stratum 4 specifications (Stratum 4). It accepts a dedicated timing reference input at either 8 kHz, 1.544 MHz or 2.048 MHz. Alternatively, the reference can be replaced by an internal 8 kHz signal derived from the ST-BUS input frame boundary. The DPLL provides reference monitor, jitter attenuation and free run functions. It can be used as a system's ST-BUS timing source which is synchronized to the network. The DPLL can also be bypassed so that the device operates under system timing.

Features. 1 Applications. 2 Description. 2 Changes Summary. 8 1.0 Device Overview. 16 2.0 Functional Description. 16 2.1 ST-BUS Input Data Rate and Input Timing. 16 2.1.1 ST-BUS Input Operation Mode. 16 2.1.2 Frame Pulse Input and Clock Input timing. 16 2.1.3 ST-BUS Input Timing. 18 2.1.4 Improved Input Jitter Tolerance with Frame Boundary Determinator. 18 2.2 ST-BUS Output Data Rate and Output Timing. 19 2.2.1 ST-BUS Output Operation Mode. 19 2.2.2 Frame Pulse Output and Clock Output Timing. 19 2.2.3 ST-BUS Output Timing. 22 2.3 Serial Data Input Delay and Serial Data Output Offset. 23 2.3.1 Input Channel Delay Programming. 23 2.3.2 Input Bit Delay Programming. 23 2.3.3 Fractional Input Bit Delay Programming. 24 2.3.4 Output Channel Delay Programming. 24 2.3.5 Output Bit Delay Programming. 25 2.3.6 Fractional Output Bit Advancement Programming. 25 2.3.7 External High Impedance Control, STOHZ 26 2.4 Data Delay Through The Switching Paths. 27 2.5 Connection Memory Description. 29 2.5.1 Connection Memory Block Programming. 29 2.6 Bit Error Rate (BER) Test. 30 2.7 Quadrant frame programming. 31 2.8 Microprocessor Port. 32 2.9 Digital Phase-Locked Loop (DPLL) Operation. 32 2.9.1 DPLL Master Mode. 33 2.9.2 DPLL Freerun Mode. 33 2.9.3 DPLL Bypass Mode. 34 2.10 DPLL Functional Description. 34 2.10.1 CKi/FPi Synchronizer and REF Select Mux. 34 2.10.2 Skew Control Circuit. 35 2.10.3 Reference Monitor Circuit. 35 2.10.4 Phase-Locked Loop (PLL) Circuit. 36 2.11 DPLL Performance. 37 2.11.1 Intrinsic Jitter. 37 2.11.2 DPLL Jitter Tolerance. 37 2.11.3 Jitter Transfer. 37 2.11.4 Frequency Accuracy. 38 2.11.5 Locking Range. 39 2.11.6 Phase Slope. 39 2.11.7 Phase Lock Time. 39 2.12 Alignment Between Input and Output Frame Pulses. 40 3.0 Oscillator Requirements. 40 3.1 External Crystal Oscillator. 40 3.2 External Clock Oscillator. 41 4.0 Device Reset and Initialization. 42


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