|Category||Communication => Network => TSI (Time Slot Interchange) => TDM/TSI Switches, Non-Blocking|
|Title||TDM/TSI Switches, Non-Blocking|
|Description||Description = Flexible 512 Channel TDM Digital Switch ;; Package Type = LQFP ;; No. Of Pins = 160|
|Datasheet||Download ZL50012 datasheet
512 channel x 512 channel non-blocking switch or 8.192Mb/s operation Rate conversion between the ST-BUS inputs and ST-BUS outputs Per-stream ST-BUS input with data rate selection or 8.192Mb/s Per-stream ST-BUS output with data rate selection or 8.192Mb/s; the output data rate can be different than the input data rate Per-stream high impedance control output for every ST-BUS output with fractional bit advancement Per-stream input channel and input bit delay programming with fractional bit delay Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay Per-channel high impedance output control
+85° C Per-channel message mode Per-channel pseudo random bit sequence (PRBS) pattern generation and bit error detection Control interface compatible to Motorola nonmultiplexed CPUs Connection memory block programming capability IEEE-1149.1 (JTAG) test port 3.3V I/O with 5V tolerant input
Small and medium digital switching platforms Access Servers Time Division Multiplexers Computer Telephony Integration Digital Loop CarriersDescription
The device has sixteen ST-BUS inputs (STi0-15) and sixteen ST-BUS outputs is a non-blocking digital switch with 512 64kb/s channels and performs rate conversion between the ST-BUS inputs and ST-BUS outputs. The ST-BUS inputs accept serial input data streams with the data rate on a per-stream basis. The ST-BUS outputs deliver serial output data streams with the data rate on a per-stream basis. The device also provides sixteen high impedance control outputs (STOHZ 0-15) to support the use of external high impedance control buffers. The ZL50012 has features that are programmable on per-stream or per-channel basis including message mode, input bit delay, output bit advancement, constant throughput delay and high impedance output control.
Features. 1 Applications. 2 Description. 2 1.0 Device Overview. 15 2.0 Functional Description. 15 2.1 ST-BUS Input Data Rate and Input Timing. 15 2.1.1 ST-BUS Input Operation Mode. 15 2.1.2 Frame Pulse Input and Clock Input timing. 15 2.1.3 ST-BUS Input Timing. 17 2.2 ST-Bus Output Data Rate and Output Timing. 18 2.2.1 ST-Bus Output Operation Mode. 18 2.2.2 Frame Pulse Output and Clock Output Timing. 18 2.2.3 ST-BUS Output Timing. 21 2.3 Serial Data Input Delay and Serial Data Output Offset. 22 2.3.1 Input Channel Delay Programming. 22 2.3.2 Input Bit Delay Programming. 22 2.3.3 Fractional Input Bit Delay Programming. 23 2.3.4 Output Channel Delay Programming. 23 2.3.5 Output Bit Delay Programming. 24 2.3.6 Fractional Output Bit Advancement Programming. 24 2.3.7 External High Impedance Control, STOHZ 25 2.4 Data Delay Through The Switching Paths. 26 2.5.1 Connection Memory Block Programming. 29 2.6 Bit Error Rate (BER) Test. 30 2.7 Quadrant frame programming. 31 2.8 Microprocessor Port. 32 3.0 Device Reset and Initialization. 32 4.0 JTAG Support. 33 4.1 Test Access Port (TAP). 33 4.2 Instruction Register. 33 4.3 Test Data Register. 33 4.4 BSDL. 33 5.0 Register Address Mapping. 34 6.0 Detail Register Description. 36
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